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Searched refs:CLK_VLP_PWM_VLP (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt8196-clock.h346 #define CLK_VLP_PWM_VLP 13 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8196-vlpckgen.c474 MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_PWM_VLP, "vlp_pwm_vlp", vlp_pwm_vlp_parents,