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Searched refs:CLK_TOP_DPI0_SEL (Results 1 – 10 of 10) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h70 #define CLK_TOP_DPI0_SEL 62 macro
H A Dmediatek,mt6795-clk.h113 #define CLK_TOP_DPI0_SEL 102 macro
H A Dmt8173-clk.h116 #define CLK_TOP_DPI0_SEL 106 macro
H A Dmediatek,mt8365-clk.h103 #define CLK_TOP_DPI0_SEL 93 macro
H A Dmt2701-clk.h104 #define CLK_TOP_DPI0_SEL 93 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c356 …MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK…
H A Dclk-mt6795-topckgen.c490 TOP_MUX_GATE_NOSR(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0xa0, 0, 3, 7, 0),
H A Dclk-mt8173-topckgen.c577 MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
H A Dclk-mt8365.c501 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0,
H A Dclk-mt2701.c527 MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,