Home
last modified time | relevance | path

Searched refs:CLK_TOP2_SENINF4 (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8196-topckgen2.c438 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF4, "seninf4", seninf_parents,
/linux/include/dt-bindings/clock/
H A Dmediatek,mt8196-clock.h159 #define CLK_TOP2_SENINF4 4 macro