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Searched refs:CLKID_VCLK_DIV2 (Results 1 – 10 of 10) sorted by relevance

/linux/include/dt-bindings/clock/
H A Daxg-clkc.h133 #define CLKID_VCLK_DIV2 123 macro
H A Dgxbb-clkc.h194 #define CLKID_VCLK_DIV2 186 macro
H A Dmeson8b-clkc.h149 #define CLKID_VCLK_DIV2 142 macro
H A Damlogic,s4-peripherals-clkc.h59 #define CLKID_VCLK_DIV2 49 macro
H A Dg12a-clkc.h160 #define CLKID_VCLK_DIV2 149 macro
/linux/drivers/clk/meson/
H A Dmeson8b.c2914 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3118 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3333 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
H A Dgxbb.c2906 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
3113 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
H A Dg12a.c4525 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4752 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
5020 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
H A Daxg.c2012 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
H A Ds4-peripherals.c3348 [CLKID_VCLK_DIV2] = &s4_vclk_div2.hw,