Home
last modified time | relevance | path

Searched refs:CCSR (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Decm.txt8 The LAW node represents the region of CCSR space where local access
10 of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
24 physical address offset and length of the CCSR space
37 The E500 LAW node represents the region of CCSR space where ECM config
39 of CCSR space.
53 physical address offset and length of the CCSR space
H A Dmcm.txt8 The LAW node represents the region of CCSR space where local access
10 of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
24 physical address offset and length of the CCSR space
37 The MPX LAW node represents the region of CCSR space where MCM config
39 of CCSR space.
53 physical address offset and length of the CCSR space
H A Dinterlaken-lac.txt43 those LAC CCSR registers not protected in partitioned
61 Definition: Points to the non-protected LAC CCSR mapped register space
H A Dmsi-pic.txt83 Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
H A Dpamu.txt32 A standard property. It represents the CCSR registers of
H A Dmpic.txt27 CCSR address space.
/linux/drivers/clk/pxa/
H A Dclk-pxa27x.c105 unsigned long ccsr = readl(clk_regs + CCSR); in pxa27x_is_ppll_disabled()
207 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_cpll_get_rate()
252 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_rate()
274 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_parent()
303 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_core_get_parent()
340 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_run_get_rate()
363 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_system_bus_get_rate()
380 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_system_bus_get_parent()
397 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_memory_get_rate()
416 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_memory_get_parent()
H A Dclk-pxa2xx.h6 #define CCSR (0x000C) /* Core Clock Status Register */ macro
/linux/arch/arm/mach-pxa/
H A Dpxa2xx-regs.h135 #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */ macro
/linux/drivers/clk/imx/
H A Dclk-imx6sl.c18 #define CCSR 0xc macro
129 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()
/linux/drivers/net/ethernet/natsemi/
H A Dns83820.c334 #define CCSR 0xcc macro
732 writel(0x0001, dev->base + CCSR); in ns83820_setup_rx()