Searched refs:BIT_3 (Results 1 – 18 of 18) sorted by relevance
278 #define IDC_FUNC_SRC_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)288 #define IDC_FUNC_3 BIT_3292 #define IDC_FC_FUNC (BIT_3 | BIT_2)302 #define IDC_RIO_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)330 #define IDC_MM_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)440 #define MBX_3 BIT_3472 #define FO1_CTIO_RETRY BIT_3528 #define FWATTRIB2_SB2 BIT_3699 #define LINK_CONFIG_LB_MODE_MASK (BIT_3 | BIT_2 | BIT_1)
163 #define BIT_3 0x8 macro350 #define QL_FL_PORT BIT_3409 #define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3505 #define ISP_FLASH_64K_BANK BIT_3 /* Flash BIOS 64K Bank Select */526 #define ISP_EN_RISC BIT_3 /* ISP enable RISC interrupts. */531 #define RISC_INT BIT_3 /* RISC interrupt */546 #define NV_DATA_IN BIT_3804 #define VPO_ENABLED BIT_31178 #define SRB_POLL BIT_3 /* Poll for completion. */1307 #define TQF_INITIATOR_DEVICE BIT_3[all …]
211 #define FLASH1024 BIT_3249 #define LED_GREEN_24 BIT_3301 #define FTYPE_FW BIT_3
87 #define CF_STAG BIT_3322 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */330 #define FCP_RESID_UNDER BIT_3343 #define SF_XFERRED_DATA BIT_3356 #define SF_SIMPLE_Q BIT_3632 #define CF_ABORT_TASK_SET BIT_31422 #define VMF_DIAGNOSTIC_FW BIT_3
87 #define ENABLE_RISC_INTR BIT_392 #define RISC_PCI_INTR_REQUEST BIT_3100 BIT_3 | BIT_2 | BIT_1)109 BIT_3 | BIT_2 | BIT_1 | BIT_0)
1438 mcp->from_fw_mask = BIT_11 | BIT_10 | BIT_3 | BIT_2 | BIT_1 | in qlt_port_online()1517 mcp->from_fw_mask |= BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_6 | BIT_7; in qlt_get_link_info()1958 mcp->to_fw_mask |= BIT_1 | BIT_3; in qlt_force_lip()2481 mcp->to_fw_mask |= BIT_2 | BIT_3 | BIT_7 | BIT_6; in qlt_alloc_mailbox_command()3625 fcp_rsp_iu[10] = (uint8_t)(fcp_rsp_iu[10] | BIT_3); in qlt_send_status()
71 #define HIGH_WARNING_BIT(_X) (BIT_3(_X))
92 #define BIT_3(_X) ((_X) & 0x08) macro
69 #define BIT_3 0x00008 macro90 #define SKD_CONFIG_SPACE_SETUP BIT_3
34 #define BIT_3 0x8 macro
388 w16 = (uint16_t)(w16 & ~(BIT_3 & BIT_2)); in ql_set_max_read_req()497 nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1; in ql_nvram_config()636 (icb->firmware_options[0] & ~BIT_3); in ql_nvram_config()644 (icb->firmware_options[0] | BIT_3); in ql_nvram_config()648 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); in ql_nvram_config()692 nv->host_p[1] & BIT_3 ? (ha->cfg_flags |= CFG_ENABLE_TARGET_RESET) : in ql_nvram_config()695 nv->adapter_features[0] & BIT_3 ? in ql_nvram_config()1018 nv->host_p[1] = BIT_3 | BIT_2; in ql_nvram_24xx_config()1126 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); in ql_nvram_24xx_config()1155 nv->host_p[1] & BIT_3 ? (ha->cfg_flags |= CFG_ENABLE_TARGET_RESET) : in ql_nvram_24xx_config()[all …]
637 nv->host_p[1] = BIT_3 | BIT_2; in ql_set_nvram_adapter_defaults()699 nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1; in ql_set_nvram_adapter_defaults()
2261 mcp->mb[10] = (uint16_t)(retry ? BIT_3 : 0); in ql_get_link_status()2266 port_no = (uint8_t)(port_no | BIT_3); in ql_get_link_status()2545 mcp->mb[1] = BIT_3; in ql_full_login_lip()
1731 } else if (pkt->entry_status & BIT_3) { in ql_error_entry()1771 if (pkt->entry_status & (BIT_5 + BIT_4 + BIT_3 + BIT_2)) { in ql_error_entry()
167 #define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3237 #define INIT_MAC_ALLOC BIT_3631 #define CFG_SUPPORT_MULTICAST BIT_3
47 #define BIT_3 0x8 macro410 #define RT_IDX_MCAST_REG_MATCH BIT_3523 #define CQ_3_NOT_EMPTY BIT_31439 #define DUMP_REQUEST_DRIVER BIT_31584 #define IDC_REQ_DEST_FUNC_3_MASK BIT_32318 #define FLASH1024 BIT_3
989 (FCOE_B2V_4(src + offset) & BIT_3) ? 1 : 0; in fcoei_fill_els_fpkt_resp()1090 (FCOE_B2V_1(src + offset) & BIT_3) ? 1 : 0; in fcoei_fill_fcp_resp()
797 ffr->ffr_flags[0] |= BIT_3; in fcoet_send_status()