Searched refs:BCM_CYGNUS_ASIU_PWM_CLK (Results 1 – 3 of 3) sorted by relevance
66 #define BCM_CYGNUS_ASIU_PWM_CLK 2 macro
247 [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10),253 [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0),
608 clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>;