Searched refs:Disabled (Results 1 – 10 of 10) sorted by relevance
50 array set BARS_size {0 {Disabled} 1 {64K} 2 {128K} 3 {256K} 4 {512K} 5 {1M} 6 {2M} 7 {4M} 8 {8M} 9 …54 array set exp_ROM_size {0 {Disabled} 1 {2K} 2 {4K} 3 {8K} 4 {16K} 5 {32K} 6 {64K} 7 {128K} 8 {256K}…59 array set fan_failure {0 {Disabled} 1 {Enabled} }62 array set en_dis {0 {Disabled} 1 {Enabled} }63 array set vf_bar2_size {0 {Disabled} 1 {4K} 2 {8K} 3 {16K} 4 {32K} 5 {64K} 6 {128K} 7 {256K} 8 {512…72 array set eee_power_mode_vals {0 {Disabled} 1 {Balanced} 2 {Aggressive} 3 {Low latency} }82 array set dcbx_mode {0 {Disabled} 1 {IEEE} 2 {CEE} 3 {Dynamic} }83 array set mgmt_traffic {0 {Disabled} 1 {NCSI over RMII} 2 {NCSI over SMBUS} }87 array set avs_mode {0 {Close Loop} 1 {Open Loop CFG} 2 {Open Loop OTP} 3 {Disabled} }88 array set sideband_mode {0 {Disabled} 1 {RMII} 2 {SGMII} }[all …]
161 if (Disabled == port->infoIs) in updtRootPrio()254 case Disabled: in updtRolesBridge()
37 Disabled enumerator
358 port->infoIs = Disabled; in STP_info_enter_state()443 if ((! port->portEnabled && port->infoIs != Disabled) || BEGIN == this->State) { in STP_info_check_conditions()
19 #Disabled by default
135 [Disabled Nov 84; it seemed to cause troubles]
19437 9500 OX16PCI954 (Quad 16950 UART) function 0 (Disabled)19451 9510 OX16PCI954 (Quad 16950 UART) function 1 (Disabled)31933 # UEFI PXE Disabled31937 # UEFI PXE Disabled31941 # PCIe x8 Bifurcated as x4x4, UEFI PXE Disabled, low profile31945 # PCIe x16 Bifurcated as x8x8, UEFI PXE Disabled, low profile
1717 1) Disabled the use of the "strchr" macro for the gcc-specific 6218 Disabled the preservation of the SCI enable bit in the PM1 control
6266 # Current Loop Disabled
7071 # Current Loop Disabled