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Searched refs:CSR_XR (Results 1 – 4 of 4) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_hlib.c211 CSR_XR(xbc_csr_base, JBUS_PARITY_CONTROL)); in jbc_init()
223 CSR_XR(xbc_csr_base, JBC_FATAL_RESET_ENABLE)); in jbc_init()
231 CSR_XR(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); in jbc_init()
237 CSR_XR(xbc_csr_base, JBC_ERROR_LOG_ENABLE)); in jbc_init()
240 CSR_XR(xbc_csr_base, JBC_INTERRUPT_ENABLE)); in jbc_init()
243 CSR_XR(xbc_csr_base, JBC_INTERRUPT_STATUS)); in jbc_init()
246 CSR_XR(xbc_csr_base, JBC_ERROR_STATUS_CLEAR)); in jbc_init()
261 CSR_XR(xbc_csr_base, UBC_ERROR_LOG_ENABLE)); in ubc_init()
268 CSR_XR(xbc_csr_base, UBC_ERROR_STATUS_CLEAR)); in ubc_init()
274 CSR_XR(xbc_csr_base, UBC_ERROR_LOG_ENABLE)); in ubc_init()
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H A Dpx_err.c756 CSR_XR(csr_base, reg_desc_p->enable_addr)); in px_err_reg_enable()
758 CSR_XR(csr_base, reg_desc_p->status_addr)); in px_err_reg_enable()
760 CSR_XR(csr_base, reg_desc_p->clear_addr)); in px_err_reg_enable()
763 CSR_XR(csr_base, reg_desc_p->log_addr)); in px_err_reg_enable()
888 ss_p->err_status[reg_id] = CSR_XR(csr_base, in px_err_snapshot()
1186 memory_ue_log = CSR_XR(csr_base, UBC_MEMORY_UE_LOG); in PX_ERPT_SEND_DEC()
1246 ubc_intr_status = CSR_XR(csr_base, UBC_INTERRUPT_STATUS); in PX_ERPT_SEND_DEC()
1265 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), in PX_ERPT_SEND_DEC()
1267 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), in PX_ERPT_SEND_DEC()
1270 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), in PX_ERPT_SEND_DEC()
[all …]
H A Dpx_csr.h37 #define CSR_XR(base, off) \ macro
H A Dpx_lib4u.c1462 return (CSR_XR((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1)); in px_get_cb()
2388 imu_log_enable = CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE); in px_cpr_callb()
2389 imu_intr_enable = CSR_XR(csr_base, IMU_INTERRUPT_ENABLE); in px_cpr_callb()
2665 *mps = CSR_XR(csr_base, TLU_DEVICE_CAPABILITIES) & in px_lib_get_root_complex_mps()
2688 dev_ctrl = CSR_XR(csr_base, TLU_DEVICE_CONTROL); in px_lib_set_root_complex_mps()