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Searched refs:sdst (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/tcsh/
H A Dtc.str.c168 Char **sdst, **dst; local
175 sdst = dst = xmalloc((n + 1) * sizeof(Char *));
180 return (sdst);
187 char **sdst, **dst; local
194 sdst = dst = xmalloc((n + 1) * sizeof(char *));
199 return (sdst);
224 static char *sdst = NULL; local
231 if (sdst == NULL) {
233 sdst = xmalloc((dstsize + MALLOC_SURPLUS) * sizeof(char));
235 dst = sdst;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSOPInstructions.td73 bits<7> sdst;
78 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
83 opName, (outs SReg_32:$sdst),
86 "$sdst, $src0", pattern> {
87 let Constraints = !if(tied_in, "$sdst = $sdst_in", "");
92 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
93 "$sdst, $src0", pattern>;
102 // Special case for movreld where sdst is treated as a use operand.
104 opName, (outs), (ins SReg_32:$sdst, SSrc_b32:$src0),
105 "$sdst, $src0", pattern>;
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H A DSMInstructions.td87 bits<7> sdst;
127 : SM_Pseudo<opName, (outs dstClass:$sdst),
129 " $sdst, $sbase, " # offsets.Asm # "$cpol", []> {
177 let Constraints = "@earlyclobber $sdst",
205 opName, (outs SReg_64_XEXEC:$sdst), (ins),
206 " $sdst", [(set i64:$sdst, (node))]> {
232 opName, (outs SReg_32_XM0_XEXEC:$sdst), (ins),
233 " $sdst", [(set i32:$sdst, (node))]> {
288 !if(isRet, (outs dataClass:$sdst), (outs)),
291 !if(isRet, " $sdst", " $sdata") #
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H A DVOPCInstructions.td78 let Outs64 = (outs VOPDstS64orS32:$sdst);
278 // This class is used only with VOPC instructions. Use $sdst for out operand
291 (inst p.DstRC:$sdst),
294 (inst p.DstRC:$sdst, p.Src0RC32:$src0),
297 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
345 [(set i1:$sdst,
354 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
900 let AsmVOP3Base = "$sdst, $src0_modifiers, $src1";
1034 (i1:$sdst
1046 (i1:$sdst
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H A DSIPeepholeSDWA.cpp1041 const MachineOperand *Sdst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in pseudoOpConvertToVOP2()
1053 MachineOperand *CarryOut = TII->getNamedOperand(MISucc, AMDGPU::OpName::sdst); in pseudoOpConvertToVOP2()
1159 const MachineOperand *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in isConvertibleToSDWA()
1170 } else if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst) || in isConvertibleToSDWA()
1220 } else if ((Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst))) { in createSDWAVersion()
1221 assert(Dst && AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::sdst)); in createSDWAVersion()
1224 assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::sdst)); in createSDWAVersion()
H A DSIInstructions.td169 def S_MOV_B64_IMM_PSEUDO : SPseudoInstSI <(outs SReg_64:$sdst),
206 def ENTER_STRICT_WWM : SPseudoInstSI <(outs SReg_1:$sdst), (ins i64imm:$src0)> {
214 def EXIT_STRICT_WWM : SPseudoInstSI <(outs SReg_1:$sdst), (ins SReg_1:$src0)> {
220 def ENTER_STRICT_WQM : SPseudoInstSI <(outs SReg_1:$sdst), (ins i64imm:$src0)> {
228 def EXIT_STRICT_WQM : SPseudoInstSI <(outs SReg_1:$sdst), (ins SReg_1:$src0)> {
237 (outs SReg_32:$sdst), (ins SSrc_b32:$mask),
238 [(set i1:$sdst, (int_amdgcn_inverse_ballot i32:$mask))]
243 (outs SReg_64:$sdst), (ins SSrc_b64:$mask),
244 [(set i1:$sdst, (int_amdgcn_inverse_ballot i64:$mask))]
312 : VPseudoInstSI<(outs SGPR_32 : $sdst),
[all …]
H A DVOPInstructions.td420 bits<7> sdst;
424 let Inst{14-8} = sdst;
711 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}}
713 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?);
714 let Inst{47} = !if(P.EmitDst, sdst{7}, 0);
1705 bits<7> sdst;
1706 let Inst{14 - 8} = sdst;
1711 bits<7> sdst;
1712 let Inst{14 - 8} = sdst;
1717 bits<8> sdst;
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H A DGCNDPPCombine.cpp131 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
252 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
H A DSIInstrInfo.td2282 (outs DstRCSDWA:$sdst),
2290 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
2335 "$sdst",
2337 ""); // use $sdst for VOPC
2364 "$sdst",
2366 ""); // use $sdst for VOPC
2442 "$sdst", // VOPC
3220 // Maps a v_cmpx opcode with sdst to opcode without sdst.
H A DSIShrinkInstructions.cpp831 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in tryReplaceDeadSDST()
1042 AMDGPU::OpName::sdst); in run()
H A DSIOptimizeExecMasking.cpp698 MachineOperand *VCmpDest = TII->getNamedOperand(*VCmp, AMDGPU::OpName::sdst); in tryRecordVCmpxAndSaveexecSequence()
H A DGCNHazardRecognizer.cpp1300 SDSTName = AMDGPU::OpName::sdst; in fixSMEMtoVectorWriteHazards()
1393 if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) in fixVcmpxExecWARHazard()
2979 const MachineOperand *SDSTOp = TII.getNamedOperand(*MI, AMDGPU::OpName::sdst); in fixVALUMaskWriteHazard()
H A DVOP2Instructions.td377 (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
656 let AsmVOP3Base = "$vdst, $sdst, $src0, $src1$clamp";
673 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
689 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
690 let AsmVOP3Base = "$vdst, $sdst, $src0, $src1, $src2$clamp";
H A DVOP3Instructions.td28 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
29 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod";
43 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
44 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
H A DSILoadStoreOptimizer.cpp1190 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
1527 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::sdst, DestReg); in mergeSMemLoadImmPair()
H A DAMDGPU.td610 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
998 def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
H A DSIInstrInfo.cpp154 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::sdst); in resultDependsOnExec()
499 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst); in getMemOperandsWithOffsetWidth()
/freebsd/crypto/openssl/providers/implementations/macs/
H A Dsiphash_prov.c76 struct siphash_data_st *sdst; in siphash_dup() local
80 sdst = OPENSSL_malloc(sizeof(*sdst)); in siphash_dup()
81 if (sdst == NULL) in siphash_dup()
84 *sdst = *ssrc; in siphash_dup()
85 return sdst; in siphash_dup()
/freebsd/sys/netinet6/
H A Dicmp6.c2324 struct sockaddr_in6 sdst; in icmp6_redirect_input() local
2331 bzero(&sdst, sizeof(sdst)); in icmp6_redirect_input()
2333 sdst.sin6_family = ssrc.sin6_family = AF_INET6; in icmp6_redirect_input()
2334 sdst.sin6_len = ssrc.sin6_len = sizeof(struct sockaddr_in6); in icmp6_redirect_input()
2335 bcopy(&reddst6, &sdst.sin6_addr, sizeof(struct in6_addr)); in icmp6_redirect_input()
2349 rib_add_redirect(fibnum, (struct sockaddr *)&sdst, gw, in icmp6_redirect_input()
/freebsd/crypto/heimdal/lib/roken/
H A Dglob.c810 Char *sdst = dst; in g_strcat() local
818 return (sdst); in g_strcat()
/freebsd/usr.sbin/route6d/
H A Droute6d.c1951 rt_del(const struct sockaddr_in6 *sdst, in rt_del() argument
1962 if (sdst->sin6_family != AF_INET6) { in rt_del()
1966 if (IN6_IS_ADDR_LINKLOCAL(&sdst->sin6_addr) in rt_del()
1967 || IN6_ARE_ADDR_EQUAL(&sdst->sin6_addr, &in6addr_loopback) in rt_del()
1968 || IN6_IS_ADDR_MULTICAST(&sdst->sin6_addr)) { in rt_del()
1970 inet6_n2p(&sdst->sin6_addr)); in rt_del()
1973 dst = &sdst->sin6_addr; in rt_del()
1991 &sdst->sin6_addr) in rt_del()
/freebsd/sys/cam/scsi/
H A Dscsi_ch.h83 uint8_t sdst[2]; /* second destination address */ member
H A Dscsi_ch.c1772 scsi_ulto2b(dst2, scsi_cmd->sdst); in scsi_exchange_medium()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp950 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) in convertSDWAInst()
954 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); in convertSDWAInst()
958 AMDGPU::OpName::sdst); in convertSDWAInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp1226 (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst) != -1); in printPackedModifier()

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