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Searched refs:regclass (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/libunwind/src/
H A DUnwind-EHABI.cpp910 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Set() argument
915 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Set()
919 switch (regclass) { in _Unwind_VRS_Set()
978 _Unwind_VRS_RegClass regclass, uint32_t regno, in _Unwind_VRS_Get_Internal() argument
982 switch (regclass) { in _Unwind_VRS_Get_Internal()
1040 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Get() argument
1044 _Unwind_VRS_Get_Internal(context, regclass, regno, representation, in _Unwind_VRS_Get()
1048 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Get()
1055 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Pop() argument
1060 static_cast<void *>(context), regclass, discriminator, in _Unwind_VRS_Pop()
[all …]
/freebsd/contrib/llvm-project/libunwind/include/
H A Dunwind_arm_ehabi.h118 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
123 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
128 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
/freebsd/contrib/libcxxrt/
H A Dunwind-arm.h132 _Unwind_VRS_RegClass regclass,
137 _Unwind_VRS_RegClass regclass,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrCDE.td471 class CDE_VCX_RegisterOperandsTemplate<RegisterClass regclass>
473 let Rd = (outs regclass:$Vd);
474 let Rd_src = (ins regclass:$Vd_src);
475 let Rn = (ins regclass:$Vn);
476 let Rm = (ins regclass:$Vm);
479 class CDE_VCXQ_RegisterOperandsTemplate<RegisterClass regclass>
481 let Rd = (outs regclass:$Qd);
482 let Rd_src = (ins regclass:$Qd_src);
483 let Rn = (ins regclass:$Qn);
484 let Rm = (ins regclass:$Qm);
H A DARMInstrInfo.td2584 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
H A DARMInstrThumb2.td1525 // can be SP. We need another regclass (similar to rGPR) to represent
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td1791 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1792 NVPTXInst<(outs regclass:$dst), (ins Offseti32imm:$b),
1796 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1797 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins Offseti32imm:$b),
1801 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1802 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1803 regclass:$dst4),
1812 …multiclass StoreParamInst<NVPTXRegClass regclass, Operand IMMType, string opstr, bit support_imm =…
1813 foreach op = [IMMType, regclass] in
1822 multiclass StoreParamV2Inst<NVPTXRegClass regclass, Operand IMMType, string opstr> {
[all …]
H A DNVPTXIntrinsics.td162 foreach regclass = ["i32", "f32"] in {
170 # "_" # regclass
206 multiclass VOTE<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
207 def : BasicNVPTXInst<(outs regclass:$dest), (ins B1:$pred),
209 [(set regclass:$dest, (IntOp i1:$pred))]>,
219 multiclass VOTE_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
220 def i : BasicNVPTXInst<(outs regclass:$dest), (ins B1:$pred, i32imm:$mask),
222 [(set regclass:$dest, (IntOp imm:$mask, i1:$pred))]>,
224 def r : BasicNVPTXInst<(outs regclass:$dest), (ins B1:$pred, B32:$mask),
226 [(set regclass:$dest, (IntOp i32:$mask, i1:$pred))]>,
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td915 /// type that it doesn't know, and resolves the actual regclass to use by using
1026 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
1029 RegisterClass RegClass = regclass;
1277 let InOperandList = (ins unknown:$src, i32imm:$regclass);
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DTargetOpcodes.def106 // pair. Once it has been lowered to a MachineInstr, the regclass operand
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td28 RegisterClass regclass,
41 def : Pat<(store (type regclass:$rs2), (XLenVT GPR:$rs1)),
H A DRISCVInstrInfoVPseudos.td169 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
172 VReg vrclass = regclass;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrUtils.td132 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
147 RegisterClass RegClass = regclass;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td307 // Condition code regclass.
H A DAArch64InstrFormats.td1253 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
1257 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
1283 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
1287 let MIOperandInfo = (ops regclass, shiftop);