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Searched refs:isSubRegisterEq (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrDesc.cpp44 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) in hasDefOfPhysReg()
49 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) in hasDefOfPhysReg()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h492 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq() function
505 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp263 if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) && in getSuperRegDestIfDead()
H A DX86InstrInfo.cpp4671 return TRI->isSubRegisterEq(NullValueReg, MO.getReg()); in preservesZeroValueInReg()
10221 if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg)) in describeLoadedValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp140 if (TRI->isSubRegisterEq(Reg, CSRegs[I]) && in canAssign()
H A DSIFrameLowering.cpp420 MRI.isAllocatable(Reg) && !TRI->isSubRegisterEq(Reg, GITPtrLoReg)) { in emitEntryFunctionFlatScratchInit()
580 (!GITPtrLoReg || !TRI->isSubRegisterEq(Reg, GITPtrLoReg))) { in getEntryFunctionReservedScratchRsrcReg()
668 TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) { in emitEntryFunctionPrologue()
676 !TRI->isSubRegisterEq(ScratchRsrcReg, Reg) && GITPtrLoReg != Reg) { in emitEntryFunctionPrologue()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp361 if (!TRI.isSubRegisterEq(AvailSrc, Reg)) in findAvailBackwardCopy()
391 if (!TRI.isSubRegisterEq(AvailDef, Reg)) in findAvailCopy()
421 if (!TRI.isSubRegisterEq(Def, Reg)) in findLastSeenDefInCopy()
H A DTargetInstrInfo.cpp230 TRI->isSubRegisterEq(ImplReg, Reg0))) in commuteInstructionImpl()
H A DRegisterCoalescer.cpp1496 TRI->isSubRegisterEq(NewMI.getOperand(0).getReg(), in reMaterializeTrivialDef()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp5500 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
5503 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
5554 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
5557 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
5586 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
5605 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
5621 if (RI->isSubRegisterEq(Rt, Rs) || in validateInstruction()
5622 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP)) in validateInstruction()
5635 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) || in validateInstruction()
5636 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP)) in validateInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp570 IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg); in restoreLatency()