| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 34 for (MCPhysReg ImpDef : implicit_defs()) in hasImplicitDefOfPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGFast.cpp | 418 assert(!MCID.implicit_defs().empty() && in getPhysicalRegisterVT()
421 for (MCPhysReg ImpDef : MCID.implicit_defs()) { in getPhysicalRegisterVT()
518 for (MCPhysReg Reg : MCID.implicit_defs()) in DelayForLiveRegsBottomUp()
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| H A D | FastISel.cpp | 2010 .addReg(II.implicit_defs()[0]); in fastEmitInst_r()
2035 .addReg(II.implicit_defs()[0]); in fastEmitInst_rr()
2062 .addReg(II.implicit_defs()[0]); in fastEmitInst_rrr()
2085 .addReg(II.implicit_defs()[0]); in fastEmitInst_ri()
2110 .addReg(II.implicit_defs()[0]); in fastEmitInst_rii()
2130 .addReg(II.implicit_defs()[0]); in fastEmitInst_f()
2156 .addReg(II.implicit_defs()[0]); in fastEmitInst_rri()
2173 .addReg(II.implicit_defs()[0]); in fastEmitInst_i()
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| H A D | InstrEmitter.cpp | 1047 bool HasPhysRegOuts = NumResults > NumDefs && !II.implicit_defs().empty() && in EmitMachineNode()
1057 II.getNumOperands() + II.implicit_defs().size() + NumImpUses && in EmitMachineNode()
1163 Register Reg = II.implicit_defs()[i - NumDefs]; in EmitMachineNode()
1203 if (!UsedRegs.empty() || !II.implicit_defs().empty() || II.hasOptionalDef()) in EmitMachineNode()
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| H A D | ScheduleDAGRRList.cpp | 1281 assert(!MCID.implicit_defs().empty() && in getPhysicalRegisterVT()
1284 for (MCPhysReg ImpDef : MCID.implicit_defs()) { in getPhysicalRegisterVT()
1435 for (MCPhysReg Reg : MCID.implicit_defs()) in DelayForLiveRegsBottomUp()
2861 TII->get(SU->getNode()->getMachineOpcode()).implicit_defs(); in canClobberReachingPhysRegUse()
2897 ArrayRef<MCPhysReg> ImpDefs = TII->get(N->getMachineOpcode()).implicit_defs(); in canClobberPhysRegDefs()
2904 TII->get(SUNode->getMachineOpcode()).implicit_defs(); in canClobberPhysRegDefs()
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| H A D | ScheduleDAGSDNodes.cpp | 468 !TII->get(N->getMachineOpcode()).implicit_defs().empty()) { in AddSchedEdges()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 581 ArrayRef<MCPhysReg> implicit_defs() const { in implicit_defs() function
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| /freebsd/contrib/llvm-project/llvm/lib/DWARFCFIChecker/ |
| H A D | DWARFCFIAnalysis.cpp | 143 getSuperReg(MCRI, MCInstInfo.implicit_defs()[I]), IsEH)); in update()
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 318 unsigned NumImplicitDefs = MCDesc.implicit_defs().size(); in populateWrites()
375 Write.RegisterID = MCDesc.implicit_defs()[CurrentDef]; in populateWrites()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 155 for (MCPhysReg R : D.implicit_defs()) in getDefsUses()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 422 unsigned NumImplicitDefs = Desc.implicit_defs().size(); in clearsSuperRegisters()
459 const MCPhysReg Reg = Desc.implicit_defs()[I]; in clearsSuperRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIShrinkInstructions.cpp | 235 MI.getDesc().implicit_defs().size(), in copyExtraImplicitOps()
654 MI.getDesc().implicit_defs().size(), in dropInstructionKeepingImpDefs()
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| H A D | AMDGPUWaitSGPRHazards.cpp | 361 llvm::any_of(MI->getDesc().implicit_defs(), isVCC); in runOnMachineBasicBlock()
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| H A D | SIFoldOperands.cpp | 1521 Desc.implicit_defs().size(); in mutateCopyOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 536 unsigned NumImplicitDefs = Desc.implicit_defs().size(); in clearsSuperRegisters()
575 const MCPhysReg Reg = Desc.implicit_defs()[I]; in clearsSuperRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 109 for (MCPhysReg R : MCID.implicit_defs()) { in init()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 338 .addReg(II.implicit_defs()[0])); in fastEmitInst_r()
365 .addReg(II.implicit_defs()[0])); in fastEmitInst_rr()
390 .addReg(II.implicit_defs()[0])); in fastEmitInst_ri()
409 .addReg(II.implicit_defs()[0])); in fastEmitInst_i()
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| H A D | Thumb2SizeReduction.cpp | 253 return is_contained(MCID.implicit_defs(), ARM::CPSR); in HasImplicitCPSRDef()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RDFGraph.cpp | 618 if (D.implicit_defs().empty() && D.implicit_uses().empty()) in isFixedReg()
628 Op.isDef() ? D.implicit_defs() : D.implicit_uses(); in isFixedReg()
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| H A D | MachineInstr.cpp | 91 for (MCPhysReg ImpDef : MCID->implicit_defs()) in addImplicitDefUseOperands()
107 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() + in MachineInstr()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 636 return getNumExplicitDefs() + MCID->implicit_defs().size();
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 1441 for (MCPhysReg ImpDef : MCID.implicit_defs()) in verifyImplicitOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 4078 .addReg(II.implicit_defs()[0]); in fastEmitInst_rrrr()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/MCParser/ |
| H A D | AsmParser.cpp | 6021 llvm::append_range(ClobberRegs, Desc.implicit_defs()); in parseMSInlineAsm()
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| H A D | MasmParser.cpp | 5974 llvm::append_range(ClobberRegs, Desc.implicit_defs()); in parseMSInlineAsm()
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