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Searched refs:getWaveMaskRegClass (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h385 const TargetRegisterClass *getWaveMaskRegClass() const { in getWaveMaskRegClass() function
H A DSILowerSGPRSpills.cpp551 const TargetRegisterClass *RC = TRI->getWaveMaskRegClass(); in run()
H A DSIFrameLowering.cpp950 MRI, LiveUnits, *TRI.getWaveMaskRegClass()); in buildScratchExecCopy()
1555 const TargetRegisterClass &RC = *TRI->getWaveMaskRegClass(); in determinePrologEpilogSGPRSaves()
H A DSIFixSGPRCopies.cpp1143 MRI->createVirtualRegister(TRI->getWaveMaskRegClass()); in fixSCCCopies()
H A DSIInstrInfo.cpp1195 const TargetRegisterClass *BoolXExecRC = RI.getWaveMaskRegClass(); in insertVectorSelect()
6583 const auto *BoolXExecRC = TRI->getWaveMaskRegClass(); in emitLoadScalarOpsFromVGPRLoop()
6732 const auto *BoolXExecRC = TRI->getWaveMaskRegClass(); in loadMBUFScalarOperandsFromVGPR()
7139 const auto *BoolXExecRC = RI.getWaveMaskRegClass(); in legalizeOperands()
7560 const auto *CarryRC = RI.getWaveMaskRegClass(); in moveToVALUImpl()
7647 Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass()); in moveToVALUImpl()
7683 Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass()); in moveToVALUImpl()
8062 const TargetRegisterClass *TC = RI.getWaveMaskRegClass(); in lowerSelect()
H A DSIRegisterInfo.cpp1179 return getWaveMaskRegClass(); in getCrossCopyRegClass()
3868 return getWaveMaskRegClass(); in getRegClassForSizeOnBank()
3911 return getWaveMaskRegClass(); in getRegClass()
H A DSIWholeQuadMode.cpp1077 MRI->constrainRegClass(ActiveLanesReg, TRI->getWaveMaskRegClass()); in lowerBlock()
H A DAMDGPUInstructionSelector.cpp445 Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass()); in selectG_ADD_SUB()
480 const TargetRegisterClass *CarryRC = TRI.getWaveMaskRegClass(); in selectG_ADD_SUB()
1130 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC()
1756 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectEndCfIntrinsic()
H A DSILoadStoreOptimizer.cpp2016 const auto *CarryRC = TRI->getWaveMaskRegClass(); in computeBase()
H A DAMDGPULegalizerInfo.cpp7393 MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
7394 MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
7429 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
H A DSIISelLowering.cpp4784 const auto *BoolXExecRC = TRI->getWaveMaskRegClass(); in loadM0FromVGPR()
5121 const TargetRegisterClass *WaveMaskRegClass = TRI->getWaveMaskRegClass(); in lowerWaveReduce()
5196 const TargetRegisterClass *WaveMaskRegClass = TRI->getWaveMaskRegClass(); in lowerWaveReduce()
5403 const auto *CarryRC = TRI->getWaveMaskRegClass(); in EmitInstrWithCustomInserter()
5650 const auto *CondRC = TRI->getWaveMaskRegClass(); in EmitInstrWithCustomInserter()
H A DAMDGPURegisterBankInfo.cpp785 const TargetRegisterClass *WaveRC = TRI->getWaveMaskRegClass(); in executeInWaterfallLoop()