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Searched refs:getSubRegFromChannel (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp210 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
215 unsigned SubRegIndex0 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction()
216 unsigned SubRegIndex1 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction()
225 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
H A DR600RegisterInfo.h27 static unsigned getSubRegFromChannel(unsigned Channel);
H A DR600RegisterInfo.cpp24 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) { in getSubRegFromChannel() function in R600RegisterInfo
H A DR600ControlFlowFinalizer.cpp279 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
288 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
H A DSIRegisterInfo.h68 /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
69 static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1); in spillSGPRToVGPR()
H A DSIShrinkInstructions.cpp614 Reg = TRI->getSubReg(Reg, TRI->getSubRegFromChannel(I)); in getSubRegForIndex()
616 Sub = TRI->getSubRegFromChannel(I + TRI->getChannelFromSubReg(Sub)); in getSubRegForIndex()
H A DSIFixSGPRCopies.cpp1082 TRI->getSubRegFromChannel(i), &AMDGPU::VGPR_32RegClass); in lowerVGPR2SGPRCopies()
1088 Result.addReg(PartialDst).addImm(TRI->getSubRegFromChannel(i)); in lowerVGPR2SGPRCopies()
H A DAMDGPUISelDAGToDAG.cpp472 unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i) in SelectBuildVector()
473 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
483 unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i) in SelectBuildVector()
484 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
3143 SIRegisterInfo::getSubRegFromChannel(i), DL, MVT::i32)); in buildRegSequence32()
H A DSIRegisterInfo.cpp541 unsigned SIRegisterInfo::getSubRegFromChannel(unsigned Channel, in getSubRegFromChannel() function in SIRegisterInfo
1545 getSubRegFromChannel(RegOffset / 4, NumRegs))); in buildSpillLoadStore()
1577 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1606 getSubRegFromChannel(RegOffset / 4, NumRegs))); in buildSpillLoadStore()
H A DSIInstrInfo.cpp764 SubIdx = RI.getSubRegFromChannel(Channel, 2); in expandSGPRCopy()
6085 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
6094 MIB.addImm(RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
6325 .addReg(VScalarOp, VScalarOpUndef, TRI->getSubRegFromChannel(Idx)); in emitLoadScalarOpsFromVGPRLoop()
6330 TRI->getSubRegFromChannel(Idx + 1)); in emitLoadScalarOpsFromVGPRLoop()
6351 TRI->getSubRegFromChannel(Idx, 2)); in emitLoadScalarOpsFromVGPRLoop()
6374 Merge.addReg(Piece).addImm(TRI->getSubRegFromChannel(Channel++)); in emitLoadScalarOpsFromVGPRLoop()
H A DR600InstrInfo.cpp59 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(I); in copyPhysReg()
H A DAMDGPUInstructionSelector.cpp522 unsigned SubReg = SIRegisterInfo::getSubRegFromChannel(Offset / 32, in selectG_EXTRACT()
807 unsigned SubReg = TRI.getSubRegFromChannel(Offset / 32, InsSize / 32); in selectG_INSERT()
3926 MIB.addImm(SIRegisterInfo::getSubRegFromChannel(i)); in buildRegSequence()
H A DSIISelLowering.cpp4612 return std::pair(SIRegisterInfo::getSubRegFromChannel(Offset), 0); in computeIndirectRegAndOffset()
15199 .addImm(SIRegisterInfo::getSubRegFromChannel(CurrIdx)); in AddMemOpInit()