| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostSelectOptimize.cpp | 179 if (MRI.getRegClassOrNull(Dst) != GPRRegClass || in foldCopyDup()
180 MRI.getRegClassOrNull(Src) != FPRRegClass) in foldCopyDup()
196 if (MRI.getRegClassOrNull(UseOp0) == FPRRegClass && in foldCopyDup()
197 MRI.getRegClassOrNull(UseOp1) == GPRRegClass) in foldCopyDup()
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| H A D | AArch64RegisterBankInfo.cpp | 1052 auto Idx = MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass in getInstrMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankSelect.cpp | 236 if (!DefReg.isValid() || MRI.getRegClassOrNull(DefReg)) in runOnMachineFunction()
263 if (MRI.getRegClassOrNull(DefReg)) in runOnMachineFunction()
279 if (!MRI.getRegClassOrNull(UseReg) || in runOnMachineFunction()
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| H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 93 if (MRI->getRegClassOrNull(DstReg)) { in markAsLaneMask()
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| H A D | AMDGPURegBankLegalize.cpp | 123 const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg); in isLaneMask()
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| H A D | AMDGPUInstructionSelector.cpp | 194 if (!MRI->getRegClassOrNull(SrcReg)) in selectCOPY()
554 if (!MRI->getRegClassOrNull(Dst1Reg)) in selectG_UADDO_USUBO_UADDE_USUBE()
1755 if (!MRI->getRegClassOrNull(Reg)) in selectEndCfIntrinsic()
2395 if (!MRI->getRegClassOrNull(CCReg)) in selectG_SELECT()
3065 if (!MRI->getRegClassOrNull(CondReg)) in selectG_BRCOND()
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| H A D | AMDGPULegalizerInfo.cpp | 2944 if (!B.getMRI()->getRegClassOrNull(PCReg)) in buildPCRelGlobalAddress()
2962 Register AddrLo = !RequiresHighHalf && !MRI.getRegClassOrNull(DstReg) in buildAbsGlobalAddress()
2966 if (!MRI.getRegClassOrNull(AddrLo)) in buildAbsGlobalAddress()
2988 Register AddrDst = !MRI.getRegClassOrNull(DstReg) in buildAbsGlobalAddress()
2992 if (!MRI.getRegClassOrNull(AddrDst)) in buildAbsGlobalAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 124 auto *RC = MRI.getRegClassOrNull(MI->getOperand(0).getReg()); in addConstantsToTrack()
125 if (!MRI.getRegClassOrNull(Reg) && RC) in addConstantsToTrack()
183 if (!MRI->getRegClassOrNull(ResVReg)) in buildOpBitcast()
370 if (!MRI.getRegClassOrNull(Reg)) in propagateSPIRVType()
432 if (!MRI.getRegClassOrNull(Reg)) in insertAssignInstr()
443 if (auto *RC = MRI.getRegClassOrNull(Reg)) { in insertAssignInstr()
485 if (!MRI.getRegClassOrNull(OpReg)) in processInstr()
613 auto *RCReg = MRI.getRegClassOrNull(Reg); in generateAssignInstrs()
614 auto *RCPrimary = MRI.getRegClassOrNull(PrimaryReg); in generateAssignInstrs()
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| H A D | SPIRVPostLegalizer.cpp | 99 bool IsKnownReg = MRI.getRegClassOrNull(ResVReg); in processNewInstrs()
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| H A D | SPIRVInstrInfo.cpp | 78 auto DefRegClass = MRI.getRegClassOrNull(MI.getOperand(0).getReg()); in isTypeDeclInstr()
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| H A D | SPIRVCallLowering.cpp | 631 if (!MRI->getRegClassOrNull(ArgReg)) { in lowerCall()
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| H A D | SPIRVUtils.cpp | 772 if (!MRI->getRegClassOrNull(Reg) || Force) { in setRegClassType()
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| H A D | SPIRVBuiltins.cpp | 604 if (MRI->getRegClassOrNull(Reg)) in setRegClassIfNull()
798 if (!MRI->getRegClassOrNull(Tmp)) in buildAtomicCompareExchangeInst()
1839 MRI->getRegClassOrNull(Call->Arguments[1])) { in generateICarryBorrowInst()
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| H A D | SPIRVInstructionSelector.cpp | 413 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in resetVRegsType()
414 const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg); in resetVRegsType()
583 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DestReg); in BuildCOPY()
584 const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg); in BuildCOPY()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InstructionSelect.cpp | 280 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in selectMachineFunction()
371 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in selectInstr()
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| H A D | Utils.cpp | 69 auto *OldRegClass = MRI.getRegClassOrNull(Reg); in constrainOperandRegClass()
95 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) { in constrainOperandRegClass()
217 return isa<const RegisterBank *>(DstRBC) && MRI.getRegClassOrNull(SrcReg) && in canReplaceReg()
219 *MRI.getRegClassOrNull(SrcReg)); in canReplaceReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MIRVRegNamerUtils.cpp | 169 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in createVirtualRegisterWithLowerName()
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| H A D | MIRCanonicalizerPass.cpp | 319 if (!MRI.getRegClassOrNull(Dst)) in propagateLocalCopies()
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| H A D | TargetRegisterInfo.cpp | 174 if (RegInfo.getRegClassOrNull(Reg)) in printRegClassOrBank()
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| H A D | MachineVerifier.cpp | 1213 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst); in verifyPreISelGenericInstruction()
1214 if (DstRC && DstRC != MRI->getRegClassOrNull(Src)) { in verifyPreISelGenericInstruction()
2655 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg); in visitMachineOperand()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 227 const TargetRegisterClass *RC = getRegClassOrNull(VReg); in shouldTrackSubRegLiveness()
662 const TargetRegisterClass *getRegClassOrNull(Register Reg) const { in getRegClassOrNull() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 1242 const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg); in simplifyCode()
1243 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg); in simplifyCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 615 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); in IsWritingToVCCR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 346 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); in selectCopy()
1625 if (!MRI.getRegClassOrNull(DstReg)) { in selectImplicitDefOrPHI()
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