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Searched refs:getPhysRegBaseClass (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h237 return isSGPRClass(getPhysRegBaseClass(Reg)); in isSGPRPhysReg()
241 return isVGPRClass(getPhysRegBaseClass(Reg)); in isVGPRPhysReg()
H A DAMDGPURewriteAGPRCopyMFMA.cpp115 const TargetRegisterClass *AssignedRC = TRI.getPhysRegBaseClass(PhysReg); in run()
H A DAMDGPUResourceUsageAnalysis.cpp422 !TRI.getPhysRegBaseClass(Reg)) && in analyzeResourceUsage()
H A DSIFrameLowering.cpp350 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in PrologEpilogSGPRSpillBuilder()
1653 const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg); in determineCalleeSaves()
1676 const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg); in determineCalleeSaves()
1761 TRI->getPhysRegBaseClass(CSI.getReg()) == &AMDGPU::VGPR_32RegClass && in assignSlotsUsingVGPRBlocks()
H A DSIFixSGPRCopies.cpp211 : TRI.getPhysRegBaseClass(SrcReg); in getCopyRegClasses()
218 : TRI.getPhysRegBaseClass(DstReg); in getCopyRegClasses()
H A DSIRegisterInfo.cpp131 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in SGPRSpillBuilder()
2702 if (isVGPRClass(getPhysRegBaseClass(MaterializedReg))) { in eliminateFrameIndex()
3598 RC = getPhysRegBaseClass(Reg); in isSGPRReg()
3700 return Reg.isVirtual() ? MRI.getRegClass(Reg) : getPhysRegBaseClass(Reg); in getRegClassForReg()
3974 assert(getRegSizeInBits(*getPhysRegBaseClass(Reg)) <= 32); in get32BitRegister()
H A DGCNHazardRecognizer.cpp1310 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) { in fixSMEMtoVectorWriteHazards()
1396 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) in fixVcmpxExecWARHazard()
H A DSIInstrInfo.cpp816 const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg); in copyPhysReg()
818 const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg); in copyPhysReg()
838 RC = RI.getPhysRegBaseClass(DestReg); in copyPhysReg()
840 SrcRC = RI.getPhysRegBaseClass(SrcReg); in copyPhysReg()
2201 bool IsAGPR = SIRegisterInfo::isAGPRClass(RI.getPhysRegBaseClass(Dst)); in expandPostRAPseudo()
5870 return RI.getPhysRegBaseClass(Reg); in getOpRegClass()
10083 RI.getPhysRegBaseClass(srcOp.getReg()); in getInstructionUniformity()
H A DSIWholeQuadMode.cpp606 TRI->hasVectorRegisters(TRI->getPhysRegBaseClass(Reg))) { in scanInstructions()
H A DAMDGPUISelDAGToDAG.cpp353 return TRI->getPhysRegBaseClass(Reg); in getOperandRegClass()
1655 const auto *RC = TRI.getPhysRegBaseClass(Reg); in IsCopyFromSGPR()
H A DSIInsertWaitcnts.cpp834 const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Op.getReg()); in getRegInterval()
H A DSIISelLowering.cpp16532 Ret.second = TRI->getPhysRegBaseClass(Ret.first); in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h782 virtual const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const { in getPhysRegBaseClass() function