Home
last modified time | relevance | path

Searched refs:ecc (Results 1 – 25 of 333) sorted by relevance

12345678910>>...14

/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Dsocfpga-eccmgr.txt8 - compatible : Should be "altr,socfpga-ecc-manager"
17 - compatible : Should be "altr,socfpga-l2-ecc"
24 - compatible : Should be "altr,socfpga-ocram-ecc"
33 compatible = "altr,socfpga-ecc-manager";
38 l2-ecc@ffd08140 {
39 compatible = "altr,socfpga-l2-ecc";
44 ocram-ecc@ffd08144 {
45 compatible = "altr,socfpga-ocram-ecc";
58 - compatible : Should be "altr,socfpga-a10-ecc-manager"
73 - compatible : Should be "altr,socfpga-a10-l2-ecc"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dmtk-nand.txt23 - ecc-engine: Required ECC Engine node.
36 ecc-engine = <&bch>;
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
65 E : nand-ecc-strength.
71 Q : nand-ecc-step-size.
75 this number depends on max ecc step size
77 If max ecc step size supported is 1024,
79 ecc step size is 512, then it should be
[all …]
H A Dhisi504-nand.txt11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
H A Dgpmc-nand.txt27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
31 "ham1" 1-bit Hamming ecc code
32 "bch4" 4-bit BCH ecc code
33 "bch8" 8-bit BCH ecc code
79 ti,nand-ecc-opt = "bch8";
113 support ecc-schemes with hardware error-correction (BCHx_HW). However
114 such SoC can use ecc-schemes with software library for error-correction
120 Other factor which governs the selection of ecc-scheme is oob-size.
131 '3' for HAM1_xx ecc schemes
[all …]
H A Dnvidia-tegra20-nand.txt25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
31 - nand-ecc-strength: integer representing the number of bits to correct
36 - nand-ecc-maximize: See nand-controller.yaml
60 nand-ecc-algo = "bch";
61 nand-ecc-strength = <8>;
H A Dtango-nand.txt29 nand-ecc-strength = <14>;
30 nand-ecc-step-size = <1024>;
35 nand-ecc-strength = <14>;
36 nand-ecc-step-size = <1024>;
H A Dvf610-nfc.txt29 - nand-ecc-mode: see nand-controller.yaml
32 - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
33 - nand-ecc-step-size: step size equals page size, currently only 2k pages are
54 nand-ecc-mode = "hw";
55 nand-ecc-strength = <32>;
56 nand-ecc-step-size = <2048>;
H A Ddavinci-nand.txt42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
48 - ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
86 nand-ecc-mode = "hw";
87 ti,davinci-ecc-bits = <4>;
H A Dmarvell-nand.txt47 - nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
48 - nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
52 the NAND chip. This value may be overwritten with nand-ecc-strength
54 - nand-ecc-strength: see nand-controller.yaml.
55 - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
78 nand-ecc-mode = "hw";
81 nand-ecc-strength = <4>;
82 nand-ecc-step-size = <512>;
H A Dmxc-nand.txt8 - nand-ecc-mode: see nand-controller.yaml
18 nand-ecc-mode = "hw";
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi349 clock-names = "nand", "nand_x", "ecc";
550 reset-names = "dwc2", "dwc2-ecc";
564 reset-names = "dwc2", "dwc2-ecc";
612 compatible = "altr,socfpga-s10-ecc-manager",
613 "altr,socfpga-a10-ecc-manager";
628 ocram-ecc@ff8cc000 {
629 compatible = "altr,socfpga-s10-ocram-ecc",
630 "altr,socfpga-a10-ocram-ecc";
632 altr,ecc-parent = <&ocram>;
636 usb0-ecc@ff8c4000 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi351 clock-names = "nand", "nand_x", "ecc";
522 reset-names = "dwc2", "dwc2-ecc";
536 reset-names = "dwc2", "dwc2-ecc";
585 compatible = "altr,socfpga-s10-ecc-manager",
586 "altr,socfpga-a10-ecc-manager";
601 ocram-ecc@ff8cc000 {
602 compatible = "altr,socfpga-s10-ocram-ecc",
603 "altr,socfpga-a10-ocram-ecc";
605 altr,ecc-parent = <&ocram>;
609 usb0-ecc@ff8c4000 {
[all …]
H A Dsocfpga_stratix10_socdk_nand.dts56 sdmmca-ecc@ff8c8c00 {
57 compatible = "altr,socfpga-s10-sdmmc-ecc",
58 "altr,socfpga-sdmmc-ecc";
60 altr,ecc-parent = <&mmc>;
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm5301x-nand-cs0-bch4.dtsi9 nand-ecc-algo = "bch";
10 nand-ecc-strength = <4>;
11 nand-ecc-step-size = <512>;
H A Dbcm5301x-nand-cs0-bch1.dtsi11 nand-ecc-algo = "bch";
12 nand-ecc-strength = <1>;
13 nand-ecc-step-size = <512>;
H A Dbcm5301x-nand-cs0-bch8.dtsi14 nand-ecc-algo = "bch";
15 nand-ecc-strength = <8>;
16 nand-ecc-step-size = <512>;
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10_socdk_sdmmc.dts19 sdmmca-ecc@ff8c2c00 {
20 compatible = "altr,socfpga-sdmmc-ecc";
22 altr,ecc-parent = <&mmc>;
H A Dsocfpga_arria10.dtsi681 clock-names = "nand", "nand_x", "ecc";
692 compatible = "altr,socfpga-a10-ecc-manager";
709 l2-ecc@ffd06010 {
710 compatible = "altr,socfpga-a10-l2-ecc";
716 ocram-ecc@ff8c3000 {
717 compatible = "altr,socfpga-a10-ocram-ecc";
723 emac0-rx-ecc@ff8c0800 {
724 compatible = "altr,socfpga-eth-mac-ecc";
726 altr,ecc-parent = <&gmac0>;
731 emac0-tx-ecc@ff8c0c00 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-linea.dtsi65 nand-ecc-mode = "hw";
66 nand-ecc-strength = <4>;
67 nand-ecc-step-size = <512>;
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun8i-r16-nintendo-nes-classic.dts39 nand-ecc-mode = "hw";
40 nand-ecc-strength = <16>;
41 nand-ecc-step-size = <1024>;
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ull-engicam-microgea.dtsi46 nand-ecc-mode = "hw";
47 nand-ecc-strength = <0>;
48 nand-ecc-step-size = <0>;
/freebsd/sys/contrib/device-tree/src/mips/ni/
H A D169445.dts63 nand-ecc-mode = "soft_bch";
64 nand-ecc-step-size = <512>;
65 nand-ecc-strength = <4>;
/freebsd/crypto/libecc/scripts/
H A Dcrossbuild.sh252 …ING" -e LADDER="$LADDER" -e CRYPTOFUZZ="$CRYPTOFUZZ" --rm -v $SRC_DIR:/ecc -w /ecc multiarch/cross…
253 …ING" -e LADDER="$LADDER" -e CRYPTOFUZZ="$CRYPTOFUZZ" --rm -v $SRC_DIR:/ecc -w /ecc/src/examples mu…
254 …ING" -e LADDER="$LADDER" -e CRYPTOFUZZ="$CRYPTOFUZZ" --rm -v $SRC_DIR:/ecc -w /ecc/src/arithmetic_…
272 …ING" -e LADDER="$LADDER" -e CRYPTOFUZZ="$CRYPTOFUZZ" --rm -v $SRC_DIR:/ecc -w /ecc multiarch/cross…
273 …ING" -e LADDER="$LADDER" -e CRYPTOFUZZ="$CRYPTOFUZZ" --rm -v $SRC_DIR:/ecc -w /ecc/src/examples mu…
274 …ING" -e LADDER="$LADDER" -e CRYPTOFUZZ="$CRYPTOFUZZ" --rm -v $SRC_DIR:/ecc -w /ecc/src/arithmetic_…
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm97xxx-nand-cs1-bch24.dtsi8 nand-ecc-strength = <24>;
9 nand-ecc-step-size = <1024>;
H A Dbcm97xxx-nand-cs1-bch4.dtsi8 nand-ecc-strength = <4>;
9 nand-ecc-step-size = <512>;

12345678910>>...14