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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DStmtNodes.td9 def Stmt : StmtNode<?, 1>;
10 def NullStmt : StmtNode<Stmt>;
11 def CompoundStmt : StmtNode<Stmt>;
12 def IfStmt : StmtNode<Stmt>;
13 def SwitchStmt : StmtNode<Stmt>;
14 def WhileStmt : StmtNode<Stmt>;
15 def DoStmt : StmtNode<Stmt>;
16 def ForStmt : StmtNode<Stmt>;
17 def GotoStmt : StmtNode<Stmt>;
18 def IndirectGotoStmt : StmtNode<Stmt>;
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H A DDeclNodes.td12 def Decl : DeclNode<?, "", 1>;
13 def TranslationUnit : DeclNode<Decl>, DeclContext;
14 def PragmaComment : DeclNode<Decl>;
15 def PragmaDetectMismatch : DeclNode<Decl>;
16 def ExternCContext : DeclNode<Decl>, DeclContext;
17 def Named : DeclNode<Decl, "named declarations", 1>;
18 def Namespace : DeclNode<Named, "namespaces">, DeclContext;
19 def UsingDirective : DeclNode<Named>;
20 def NamespaceAlias : DeclNode<Named>;
21 def Label : DeclNode<Named, "labels">;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUs
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td9 /// Define scheduler resources associated with def operands.
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide
17 def WriteIDiv32 : SchedWrite; // 32-bit divide on RV64I
18 def WriteIRem : SchedWrite; // 32-bit or 64-bit remainder
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H A DRISCVSchedTTAscalonD8.td11 def TTAscalonD8Model : SchedMachineModel {
32 def AscalonLS : ProcResource<3>;
33 def AscalonFXA : ProcResource<1>; // ALU, FP/VEC -> INT, MUL, DIV, CSR
34 def AscalonFXB : ProcResource<1>; // ALU, INT -> FP/VEC
35 def AscalonFXC : ProcResource<2>; // ALU, BR
36 def AscalonFXD : ProcResource<2>; // ALU
37 def AscalonFP : ProcResource<2>;
41 def AscalonFX : ProcResGroup<[AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXD]>;
46 def : WriteRes<WriteJmp, [AscalonFXC]>;
47 def : WriteRes<WriteJal, [AscalonFXC]>;
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H A DRISCVSchedAndes45.td12 def Andes45Model : SchedMachineModel {
38 def Andes45ALU : ProcResource<2>;
39 def Andes45MDU : ProcResource<1>;
40 def Andes45LSU : ProcResource<1>;
41 def Andes45CSR : ProcResource<1>;
43 def Andes45FMAC : ProcResource<1>;
44 def Andes45FDIV : ProcResource<1>;
45 def Andes45FMV : ProcResource<1>;
46 def Andes45FMISC : ProcResource<1>;
50 def : WriteRes<WriteIALU, [Andes45ALU]>;
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H A DRISCVSchedSiFiveP500.td11 def SiFiveP500Model : SchedMachineModel {
26 def SiFiveP500IEXQ0 : ProcResource<1>;
27 def SiFiveP500IEXQ1 : ProcResource<1>;
28 def SiFiveP500IEXQ2 : ProcResource<1>;
29 def SiFiveP500FEXQ0 : ProcResource<1>;
30 def SiFiveP500FEXQ1 : ProcResource<1>;
31 def SiFiveP500Load : ProcResource<1>;
32 def SiFiveP500Store : ProcResource<1>;
34 def SiFiveP500IntArith : ProcResGroup<[SiFiveP500IEXQ0, SiFiveP500IEXQ1, SiFiveP500IEXQ2]>;
39 def SiFiveP500Div : ProcResource<1>;
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H A DRISCVSchedGenericOOO.td30 def GenericOOOModel : SchedMachineModel {
42 def GenericOOOBranch : ProcResource<1>;
43 def GenericOOOMulDiv : ProcResource<1>;
44 def GenericOOOInt : ProcResource<2>;
45 def GenericOOOALU
47 def GenericOOOLSU : ProcResource<2>;
48 def GenericOOOFMulDiv : ProcResource<1>;
49 def GenericOOOFloat : ProcResource<1>;
50 def GenericOOOFPU : ProcResGroup<[GenericOOOFMulDiv, GenericOOOFloat]>;
55 def : WriteRes<WriteJmp, [GenericOOOBranch]>;
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H A DRISCVSchedXiangShanNanHu.td19 def XiangShanNanHuModel : SchedMachineModel {
34 def XS2ALU : ProcResource<4>;
35 def XS2MDU : ProcResource<2>;
36 def XS2MISC : ProcResource<1>;
38 def XS2FMAC : ProcResource<4>;
39 def XS2FMISC : ProcResource<2>;
42 def XS2LD : ProcResource<2>;
43 def XS2ST : ProcResource<2>;
47 def : WriteRes<WriteJmp, [XS2MISC]>;
48 def : WriteRes<WriteJal, [XS2MISC]>;
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H A DRISCVSchedMIPSP8700.td20 def MIPSP8700Model : SchedMachineModel {
31 def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
34 def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
35 def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
36 def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
37 def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }
38 def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;
41 def p8700GpDiv : ProcResource<1>;
42 def p8700GpMul : ProcResource<1>;
44 def : WriteRes<WriteIALU, [p8700WriteEitherALU]>;
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H A DRISCVSchedSpacemitX60.td16 def SpacemitX60Model : SchedMachineModel {
36 def SMX60_LS : ProcResource<2>;
39 def SMX60_IEUA : ProcResource<1>;
40 def SMX60_IEUB : ProcResource<1>;
41 def SMX60_IEU : ProcResGroup<[SMX60_IEUA, SMX60_IEUB]>;
46 def SMX60_FP : ProcResource<1>;
52 def : WriteRes<WriteJmp, [SMX60_IEUA]>;
53 def : WriteRes<WriteJal, [SMX60_IEUA]>;
54 def : WriteRes<WriteJalr, [SMX60_IEUA]>;
58 def : WriteRes<WriteIALU32, [SMX60_IEU]>;
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H A DRISCVSchedSyntacoreSCR7.td17 def SyntacoreSCR7Model : SchedMachineModel {
29 def : WriteRes<WriteJmp, [BRU]>;
30 def : WriteRes<WriteJal, [BRU]>;
31 def : WriteRes<WriteJalr, [BRU]>;
36 def : WriteRes<WriteIALU, [ALU]>;
37 def : WriteRes<WriteIALU32, [ALU]>;
38 def : WriteRes<WriteShiftImm, [ALU]>;
39 def : WriteRes<WriteShiftImm32, [ALU]>;
40 def : WriteRes<WriteShiftReg, [ALU]>;
41 def : WriteRes<WriteShiftReg32, [ALU]>;
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H A DRISCVScheduleZb.td9 /// Define scheduler resources associated with def operands.
12 def WriteSHXADD : SchedWrite; // sh1add/sh2add/sh3add
13 def WriteSHXADD32 : SchedWrite; // sh1add.uw/sh2add.uw/sh3add.uw
16 def WriteRotateImm : SchedWrite;
17 def WriteRotateImm32 : SchedWrite;
18 def WriteRotateReg : SchedWrite;
19 def WriteRotateReg32 : SchedWrite;
20 def WriteCLZ : SchedWrite;
21 def WriteCLZ32 : SchedWrite;
22 def WriteCTZ : SchedWrite;
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H A DRISCVSchedRocket.td14 def RocketModel : SchedMachineModel {
33 def RocketUnitALU : ProcResource<1>; // Int ALU
34 def RocketUnitIMul : ProcResource<1>; // Int Multiply
35 def RocketUnitMem : ProcResource<1>; // Load/Store
36 def RocketUnitB : ProcResource<1>; // Branch
38 def RocketUnitFPALU : ProcResource<1>; // FP ALU
42 def RocketUnitIDiv : ProcResource<1>; // Int Division
43 def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
51 def : WriteRes<WriteJmp, [RocketUnitB]>;
52 def : WriteRes<WriteJal, [RocketUnitB]>;
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsHexagonDep.td1063 def int_hexagon_A2_abs :
1066 def int_hexagon_A2_absp :
1069 def int_hexagon_A2_abssat :
1072 def int_hexagon_A2_add :
1075 def int_hexagon_A2_addh_h16_hh :
1078 def int_hexagon_A2_addh_h16_hl :
1081 def int_hexagon_A2_addh_h16_lh :
1084 def int_hexagon_A2_addh_h16_ll :
1087 def int_hexagon_A2_addh_h16_sat_hh :
1090 def int_hexagon_A2_addh_h16_sat_hl :
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H A DRuntimeLibcalls.td19 def isOSDarwin : RuntimeLibcallPredicate<"TT.isOSDarwin()">;
20 def isOSOpenBSD : RuntimeLibcallPredicate<"TT.isOSOpenBSD()">;
21 def isOSWindows : RuntimeLibcallPredicate<"TT.isOSWindows()">;
22 def isNotOSWindows : RuntimeLibcallPredicate<"!TT.isOSWindows()">;
23 def isNotOSMSVCRT : RuntimeLibcallPredicate<"!TT.isOSMSVCRT()">;
24 def isPS : RuntimeLibcallPredicate<"TT.isPS()">;
25 def isNotOSWindowsOrIsCygwinMinGW
29 def isGNUEnvironment : RuntimeLibcallPredicate<"TT.isGNUEnvironment()">;
30 def darwinHasSinCosStret : RuntimeLibcallPredicate<"darwinHasSinCosStret(TT)">;
31 def darwinHasExp10 : RuntimeLibcallPredicate<"darwinHasExp10(TT)">;
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H A DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
26 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
28 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
35 def int_aarch64_clrex : Intrinsic<[]>;
37 def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrInfo.td19 def MOVGR2SCR : FmtGR2SCR<0x00000800>;
20 def MOVSCR2GR : FmtSCR2GR<0x00000c00>;
22 def JISCR0 : FmtJISCR<0x48000200>;
23 def JISCR1 : FmtJISCR<0x48000300>;
25 def ADDU12I_W : ALU_2RI5<0x00290000, simm5>;
27 def ADC_B : ALU_3R<0x00300000>;
28 def ADC_H : ALU_3R<0x00308000>;
29 def ADC_W : ALU_3R<0x00310000>;
31 def SBC_B : ALU_3R<0x00320000>;
32 def SBC_H : ALU_3R<0x00328000>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsicsV5.td9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
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/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRDevices.td34 def FeatureSRAM : SubtargetFeature<"sram", "HasSRAM", "true",
38 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "HasJMPCALL", "true",
43 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "HasSRAMIJMPCALL", "true",
48 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "HasEIJMPCALL", "true",
53 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "HasADDSUBIW", "true",
58 def FeatureSmallStack
70 def FeatureWrappingRjmp
76 def FeatureMOVW : SubtargetFeature<"movw", "HasMOVW", "true",
81 def FeatureLPM : SubtargetFeature<"lpm", "HasLPM", "true",
85 def FeatureLPMX : SubtargetFeature<"lpmx", "HasLPMX", "true",
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSearchableTables.td19 def RsrcIntrinsics : GenericTable {
30 def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
51 def Gfx9BufferFormat : GcnBufferFormatTable {
55 def Gfx10BufferFormat : GcnBufferFormatTable {
59 def Gfx11PlusBufferFormat : GcnBufferFormatTable {
64 def getGfx9BufferFormatInfo : SearchIndex {
68 def getGfx10BufferFormatInfo : SearchIndex {
72 def getGfx11PlusBufferFormatInfo : SearchIndex {
78 def : Gfx9BufferFormat< /*FORMAT_8_UNORM*/ 0x01, 8, 1, /*NUM_FORMAT_UNORM*/ 0, /*DA…
79 def : Gfx9BufferFormat< /*FORMAT_8_SNORM*/ 0x11, 8, 1, /*NUM_FORMAT_SNORM*/ 1, /*DA…
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td49 def : GINodeEquiv<G_ANYEXT, anyext>;
50 def : GINodeEquiv<G_SEXT, sext>;
51 def : GINodeEquiv<G_SEXT_INREG, sext_inreg>;
52 def : GINodeEquiv<G_ZEXT, zext>;
53 def : GINodeEquiv<G_TRUNC, trunc>;
54 def : GINodeEquiv<G_BITCAST, bitconvert>;
57 def : GINodeEquiv<G_CONSTANT, imm>;
59 def : GINodeEquiv<G_FCONSTANT, fpimm>;
60 def : GINodeEquiv<G_IMPLICIT_DEF, undef>;
61 def : GINodeEquiv<G_FRAME_INDEX, frameindex>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSchedule.td12 def ALU : FuncUnit;
13 def IMULDIV : FuncUnit;
19 def IIM16Alu : InstrItinClass;
20 def IIPseudo : InstrItinClass;
22 def II_ABS : InstrItinClass;
23 def II_ADDI : InstrItinClass;
24 def II_ADDIU : InstrItinClass;
25 def II_ADDIUPC : InstrItinClass;
26 def II_ADD : InstrItinClass;
27 def II_ADDU : InstrItinClass;
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