| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4987 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in WidenVecRes_Ternary() local
4992 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3); in WidenVecRes_Ternary()
4998 GetWidenedMask(N->getOperand(3), WidenVT.getVectorElementCount()); in WidenVecRes_Ternary()
4999 return DAG.getNode(N->getOpcode(), dl, WidenVT, in WidenVecRes_Ternary()
5006 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in WidenVecRes_Binary() local
5010 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, in WidenVecRes_Binary()
5017 GetWidenedMask(N->getOperand(2), WidenVT.getVectorElementCount()); in WidenVecRes_Binary()
5018 return DAG.getNode(N->getOpcode(), dl, WidenVT, in WidenVecRes_Binary()
5047 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in WidenVecRes_BinaryWithExtraScalarOp() local
5051 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3, in WidenVecRes_BinaryWithExtraScalarOp()
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| H A D | SelectionDAGBuilder.cpp | 719 EVT WidenVT = in getCopyToPartsVector() local
722 SDValue Widened = widenVectorToPartType(DAG, Val, DL, WidenVT); in getCopyToPartsVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4342 MVT WidenVT = getTypeToTransformTo(*DAG.getContext(), VT).getSimpleVT(); in ReplaceNodeResults() local
4348 unsigned WidenNumElts = WidenVT.getVectorNumElements(); in ReplaceNodeResults()
4351 if ((128 % InBits) == 0 && WidenVT.is128BitVector()) { in ReplaceNodeResults()
4364 assert(isTypeLegal(WidenVT) && isTypeLegal(WidenIn.getValueType()) && in ReplaceNodeResults()
4366 WidenIn = DAG.getBitcast(WidenVT, WidenIn); in ReplaceNodeResults()
4368 DAG.getVectorShuffle(WidenVT, DL, WidenIn, WidenIn, TruncMask)); in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5699 MVT WidenVT = MVT::getVectorVT(MVT::i8, VT.getVectorElementCount()); in lowerVECTOR_SHUFFLE() local
5700 V1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V1); in lowerVECTOR_SHUFFLE()
5701 V2 = V2.isUndef() ? DAG.getUNDEF(WidenVT) in lowerVECTOR_SHUFFLE()
5702 : DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V2); in lowerVECTOR_SHUFFLE()
5703 SDValue Shuffled = DAG.getVectorShuffle(WidenVT, DL, V1, V2, SVN->getMask()); in lowerVECTOR_SHUFFLE()
5704 return DAG.getSetCC(DL, VT, Shuffled, DAG.getConstant(0, DL, WidenVT), in lowerVECTOR_SHUFFLE()
12247 MVT WidenVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorElementCount()); in lowerVECTOR_REVERSE() local
12248 SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, Op.getOperand(0)); in lowerVECTOR_REVERSE()
12249 SDValue Op2 = DAG.getNode(ISD::VECTOR_REVERSE, DL, WidenVT, Op1); in lowerVECTOR_REVERSE()
13469 MVT WidenVT = ContainerVT.changeVectorElementType(MVT::i8); in lowerVPSplatExperimental() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 33962 MVT WidenVT = getTypeToTransformTo(*DAG.getContext(), VT).getSimpleVT(); in ReplaceNodeResults() local
33968 unsigned WidenNumElts = WidenVT.getVectorNumElements(); in ReplaceNodeResults()
33977 Res = widenSubVector(WidenVT, Res, false, Subtarget, DAG, dl); in ReplaceNodeResults()
33983 if ((128 % InBits) == 0 && WidenVT.is128BitVector()) { in ReplaceNodeResults()
33992 assert(isTypeLegal(WidenVT) && isTypeLegal(WidenIn.getValueType()) && in ReplaceNodeResults()
33994 WidenIn = DAG.getBitcast(WidenVT, WidenIn); in ReplaceNodeResults()
33996 DAG.getVectorShuffle(WidenVT, dl, WidenIn, WidenIn, TruncMask)); in ReplaceNodeResults()
34007 Results.push_back(DAG.getNode(X86ISD::VTRUNC, dl, WidenVT, In)); in ReplaceNodeResults()
34014 Results.push_back(DAG.getNode(X86ISD::VTRUNC, dl, WidenVT, In)); in ReplaceNodeResults()
34044 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, WidenVT, WidenIn)); in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6666 MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts); in LowerCTPOP() local
6667 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, WidenVT, Ops); in LowerCTPOP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10816 MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts); in LowerCTPOP_PARITY() local
10817 Val = DAG.getNode(AArch64ISD::UADDLP, DL, WidenVT, Val); in LowerCTPOP_PARITY()
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