| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 50 unsigned ValueReg, unsigned Address,
56 unsigned ValueReg, unsigned Address,
247 unsigned ValueReg, unsigned Address,
255 unsigned ValueReg, unsigned Address,
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| H A D | R600InstrInfo.cpp | 1078 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1080 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1085 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1101 AddrReg, ValueReg) in buildIndirectWrite()
1110 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1112 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectRead()
1117 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1133 ValueReg, in buildIndirectRead()
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| H A D | SIRegisterInfo.cpp | 1452 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
1466 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1467 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1470 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()
1571 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1590 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
1788 ? ValueReg in buildSpillLoadStore()
1789 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1822 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1823 : ValueReg; in buildSpillLoadStore()
[all …]
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| H A D | SIRegisterInfo.h | 463 unsigned LoadStoreOp, int Index, Register ValueReg,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVBuiltins.cpp | 384 Register ValueReg = BitcastMI->getOperand(2).getReg(); in getBlockStructInstr() local
385 MachineInstr *ValueMI = MRI->getUniqueVRegDef(ValueReg); in getBlockStructInstr()
408 Register ValueReg = MI->getOperand(0).getReg(); in getMachineInstrType() local
411 NextMI->getOperand(1).getReg() != ValueReg) in getMachineInstrType()
842 Register ValueReg = Call->Arguments[1]; in buildAtomicRMWInst() local
853 MRI->createGenericVirtualRegister(MRI->getType(ValueReg)); in buildAtomicRMWInst()
859 .addUse(ValueReg); in buildAtomicRMWInst()
862 ValueReg = NegValueReg; in buildAtomicRMWInst()
871 .addUse(ValueReg); in buildAtomicRMWInst()
885 Register ValueReg = Call->Arguments[3]; in buildAtomicFloatingRMWInst() local
[all …]
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| H A D | SPIRVInstructionSelector.cpp | 1347 Register ValueReg = I.getOperand(2).getReg(); in selectAtomicRMW() local
1351 Result &= selectOpWithSrcs(TmpReg, ResType, I, {ValueReg}, NegateOpcode); in selectAtomicRMW()
1352 ValueReg = TmpReg; in selectAtomicRMW()
1362 .addUse(ValueReg) in selectAtomicRMW()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode() local
185 const LLT Ty = MRI.getType(ValueReg); in selectLoadStoreOpCode()
192 if (isRegInGprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
222 if (isRegInFprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 1304 Register ValueReg = getRegForValue(Store->getValueOperand()); in selectStore() local
1305 if (ValueReg == 0) in selectStore()
1308 ValueReg = maskI1Value(ValueReg, Store->getValueOperand()); in selectStore()
1314 MIB.addReg(ValueReg); in selectStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13053 Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitPartwordAtomicBinary() local
13054 BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg) in EmitPartwordAtomicBinary()
13056 MI.getOperand(3).setReg(ValueReg); in EmitPartwordAtomicBinary()
13057 incr = ValueReg; in EmitPartwordAtomicBinary()
13200 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary() local
13203 ValueReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
13204 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg) in EmitPartwordAtomicBinary()
13209 .addReg(ValueReg); in EmitPartwordAtomicBinary()
13210 ValueReg = ValueSReg; in EmitPartwordAtomicBinary()
13213 BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ValueReg).addReg(CmpReg); in EmitPartwordAtomicBinary()
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