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Searched refs:VGPR (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td30 !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
41 !foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
55 !foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
67 !foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
73 (add (sequence "VGPR%u", 40, 47),
74 (sequence "VGPR%u", 56, 63),
75 (sequence "VGPR%u", 72, 79),
76 (sequence "VGPR%u", 88, 95),
77 (sequence "VGPR%u", 104, 111),
78 (sequence "VGPR%u", 120, 127),
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H A DGCNRegPressure.h32 enum RegKind { SGPR, VGPR, AGPR, TOTAL_KINDS }; enumerator
38 bool empty() const { return !Value[SGPR] && !Value[VGPR] && !Value[AGPR]; } in empty()
48 return Value[AGPR] ? getUnifiedVGPRNum(Value[VGPR], Value[AGPR]) in getVGPRNum()
49 : Value[VGPR]; in getVGPRNum()
51 return std::max(Value[VGPR], Value[AGPR]); in getVGPRNum()
63 unsigned getArchVGPRNum() const { return Value[VGPR]; } in getArchVGPRNum()
68 return std::max(Value[TOTAL_KINDS + VGPR], Value[TOTAL_KINDS + AGPR]); in getVGPRTuplesWeight()
H A DSIRegisterInfo.td312 // VGPR registers
314 defm VGPR#Index :
373 // Give all SGPR classes higher priority than VGPR classes, because
576 (add (interleave (sequence "VGPR%u_LO16", 0, 255),
577 (sequence "VGPR%u_HI16", 0, 255)))> {
582 // This is the base class for VGPR{128..255}_{LO16,HI16}.
590 (add (interleave (sequence "VGPR%u_LO16", 0, 127),
591 (sequence "VGPR%u_HI16", 0, 127)))> {
596 // This is the base class for VGPR{0..127}_{LO16,HI16}.
600 // VGPR 32-bit registers
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H A DSIRegisterInfo.h65 Register VGPR; member
69 SpilledReg(Register R, int L) : VGPR(R), Lane(L) {} in SpilledReg()
72 bool hasReg() { return VGPR != 0; } in hasReg()
111 static bool isChainScratchRegister(Register VGPR);
H A DSILowerSGPRSpills.cpp312 if (PrevLaneVGPR == Spill.VGPR) in updateLaneVGPRDomInstr()
315 PrevLaneVGPR = Spill.VGPR; in updateLaneVGPRDomInstr()
316 auto I = LaneVGPRDomInstr.find(Spill.VGPR); in updateLaneVGPRDomInstr()
319 LaneVGPRDomInstr[Spill.VGPR] = InsertPt; in updateLaneVGPRDomInstr()
H A DAMDGPURegisterBanks.td13 def VGPRRegBank : RegisterBank<"VGPR",
H A DSIMachineFunctionInfo.cpp291 void SIMachineFunctionInfo::allocateWWMSpill(MachineFunction &MF, Register VGPR, in allocateWWMSpill() argument
294 if (isEntryFunction() || WWMSpills.count(VGPR)) in allocateWWMSpill()
307 (SIRegisterInfo::isChainScratchRegister(VGPR) || in allocateWWMSpill()
312 VGPR, MF.getFrameInfo().CreateSpillStackObject(Size, Alignment))); in allocateWWMSpill()
H A DSIFrameLowering.cpp108 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
279 Spill[I].VGPR) in saveToVGPRLane()
282 .addReg(Spill[I].VGPR, RegState::Undef); in saveToVGPRLane()
326 .addReg(Spill[I].VGPR) in restoreFromVGPRLane()
991 Register VGPR = Reg.first; in emitCSRSpillStores() local
994 VGPR, FI, FrameReg); in emitCSRSpillStores()
1094 Register VGPR = Reg.first; in emitCSRSpillRestores() local
1097 VGPR, FI, FrameReg); in emitCSRSpillRestores()
H A DSIInstrInfo.td103 SDTCisVT<2, i32>, // vindex(VGPR)
104 SDTCisVT<3, i32>, // voffset(VGPR)
121 SDTCisVT<2, i32>, // vindex(VGPR)
122 SDTCisVT<3, i32>, // voffset(VGPR)
139 SDTCisVT<2, i32>, // vindex(VGPR)
140 SDTCisVT<3, i32>, // voffset(VGPR)
177 SDTCisVT<2, i32>, // vindex(VGPR)
178 SDTCisVT<3, i32>, // voffset(VGPR)
203 SDTCisVT<3, i32>, // vindex(VGPR)
204 SDTCisVT<4, i32>, // voffset(VGPR)
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H A DAMDGPUGenRegisterBankInfo.def70 {0, 1, VGPRRegBank}, // VGPR begin
H A DSIPeepholeSDWA.cpp1374 Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in legalizeScalarOperands() local
1376 TII->get(AMDGPU::V_MOV_B32_e32), VGPR); in legalizeScalarOperands()
1382 Op.ChangeToRegister(VGPR, false); in legalizeScalarOperands()
H A DSISchedule.td369 // Add 1 stall cycle for VGPR read.
402 // Add 1 stall cycle for VGPR read.
H A DAMDGPU.td313 …"Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of…
571 "Has VGPR mode register indexing"
1106 "VMEM instructions of the same type write VGPR results in order"
1318 "Enable dynamic VGPR mode"
1325 "Use a block size of 32 for dynamic VGPR allocation (default is 16)"
1333 "Use block load/store for VGPR callee saved registers"
H A DSIRegisterInfo.cpp452 bool SIRegisterInfo::isChainScratchRegister(Register VGPR) { in isChainScratchRegister() argument
453 return VGPR >= AMDGPU::VGPR0 && VGPR < AMDGPU::VGPR8; in isChainScratchRegister()
2073 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR) in spillSGPR()
2076 .addReg(Spill.VGPR); in spillSGPR()
2183 .addReg(Spill.VGPR) in restoreSGPR()
H A DVOP1Instructions.td391 // Restrict src0 to be VGPR
836 // Restrict src0 to be VGPR
1491 // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
1499 // Copy of v_mov_b32 for use with VGPR indexing mode. An implicit use of the
H A DSIInstructions.td143 // 32-bit materialize immediate which supports AGPR or VGPR. Typically
785 // Match dynamic VGPR case. This is always indirect since we choose the callee
786 // dynamically based on the result of the VGPR reallocation, so make sure to
931 // These variants of V_INDIRECT_REG_READ/WRITE use VGPR indexing. By using these
933 // that switch the VGPR indexing mode. Spills to accvgprs could be effected by
1038 // VGPR or AGPR spill instructions. In case of AGPR spilling a temp register
1039 // needs to be used and an extra instruction to move between VGPR and AGPR.
2176 // unnecessary copy from SGPR to VGPR.
3754 // Avoid pointlessly materializing a constant in VGPR.
H A DSIInstrFormats.td49 // Combined SGPR/VGPR spill bit
H A DSIMachineFunctionInfo.h768 void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size = 4,
H A DVOP3PInstructions.td811 // Does this MFMA use "AGPR" or "VGPR" for srcC/vdst
923 MFMATable<0, "VGPR", NAME # "_vgprcd_e64", NAME # "_e64">;
937 MFMATable<1, "VGPR", NAME # "_vgprcd_e64", NAME # "_mac_e64">;
958 MFMATable<0, "VGPR", NAME # "_vgprcd_e64", NAME # "_e64">;
970 MFMATable<1, "VGPR", NAME # "_vgprcd_e64", NAME # "_mac_e64">;
H A DGCNRegPressure.cpp41 return STI->isSGPRClass(RC) ? SGPR : (STI->isAGPRClass(RC) ? AGPR : VGPR); in getRegKind()
H A DVOP3Instructions.td561 // blocking folding SGPR->VGPR copies later.
897 // GISel-specific pattern that avoids creating a SGPR->VGPR copy if
898 // $src2 is a VGPR.
1180 // All convert opcodes operating on FP6/BF6/FP4 data must use VGPR sources for
H A DVOPInstructions.td510 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction.
H A DFLATInstructions.td68 bits<1> has_sve = 0; // Scratch VGPR Enable
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td587 // The pointer argument is assumed to be dynamically uniform if a VGPR.
1076 P_.RetTypes, // vdata(VGPR) -- for load/atomic-with-return
1078 !foreach(arg, P_.DataArgs, arg.Type), // vdata(VGPR) -- for store/atomic
1080 P_.AddrTypes, // vaddr(VGPR)
1361 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
1378 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
1391 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
1409 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
1422 llvm_i32_ty, // vindex(VGPR)
1423 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
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