| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 767 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
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| H A D | SystemZISelLowering.cpp | 7644 const SDLoc &DL, EVT TruncVT, SDValue Op, DAGCombinerInfo &DCI) const { in combineTruncateExtract() argument
7649 TruncVT.getSizeInBits() % 8 == 0) { in combineTruncateExtract()
7655 unsigned TruncBytes = TruncVT.getStoreSize(); in combineTruncateExtract()
7670 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT); in combineTruncateExtract()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 7298 EVT TruncVT = TLI->getValueType(*DL, I->getType()); in optimizeLoadExt() local
7299 unsigned TruncBitWidth = TruncVT.getSizeInBits(); in optimizeLoadExt()
7328 EVT TruncVT = TLI->getValueType(*DL, TruncTy); in optimizeLoadExt() local
7331 if (!LoadResultVT.bitsGT(TruncVT) || !TruncVT.isRound() || in optimizeLoadExt()
7332 !TLI->isLoadExtLegal(ISD::ZEXTLOAD, LoadResultVT, TruncVT)) in optimizeLoadExt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1148 bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT,
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| H A D | X86ISelLowering.cpp | 10612 MVT TruncVT = MVT::getVectorVT(DstSVT, NumSrcElts); in getAVX512TruncNode() local
10613 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Src); in getAVX512TruncNode()
10618 MVT TruncVT = MVT::getVectorVT(DstSVT, NumSrcElts); in getAVX512TruncNode() local
10619 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Src); in getAVX512TruncNode()
10632 MVT TruncVT = MVT::getVectorVT(DstSVT, 128 / DstEltSizeInBits); in getAVX512TruncNode() local
10633 SDValue Trunc = DAG.getNode(X86ISD::VTRUNC, DL, TruncVT, Src); in getAVX512TruncNode()
10634 if (DstVT != TruncVT) in getAVX512TruncNode()
21324 MVT TruncVT = MVT::getVectorVT(MVT::i32, NumElems); in LowerTruncateVecPack() local
21325 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, In); in LowerTruncateVecPack()
21599 MVT TruncVT = MVT::v4i1; in LowerFP_TO_INT() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 10219 EVT TruncVT = N->getValueType(0); in distributeTruncateThroughAnd() local
10221 TLI.isTypeDesirableForOp(ISD::AND, TruncVT)) { in distributeTruncateThroughAnd()
10226 SDValue Trunc00 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00); in distributeTruncateThroughAnd()
10227 SDValue Trunc01 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N01); in distributeTruncateThroughAnd()
10230 return DAG.getNode(ISD::AND, DL, TruncVT, Trunc00, Trunc01); in distributeTruncateThroughAnd()
10838 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue()); in visitSRA() local
10841 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorElementCount()); in visitSRA()
10851 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && in visitSRA()
10853 TLI.isTruncateFree(VT, TruncVT)) { in visitSRA()
10857 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, in visitSRA()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1727 EVT TruncVT = EVT::getVectorVT(*DAG.getContext(), in PromoteIntRes_TRUNCATE() local
1729 SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp); in PromoteIntRes_TRUNCATE()
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| H A D | LegalizeVectorTypes.cpp | 6426 EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(), in convertMask() local
6428 Mask = DAG.getNode(ISD::TRUNCATE, SDLoc(Mask), TruncVT, Mask); in convertMask()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 953 virtual bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) const { in preferSextInRegOfTruncate() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10884 EVT TruncVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); in widenLoad() local
10888 TruncVT = MemVT.changeTypeToInteger(); in widenLoad()
10894 DAG.getValueType(TruncVT)); in widenLoad()
10897 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 28962 EVT TruncVT = ContainerVT.changeVectorElementType( in LowerFixedLengthVectorStoreToSVE() local
28965 NewValue = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, TruncVT, Pg, in LowerFixedLengthVectorStoreToSVE()
28967 DAG.getUNDEF(TruncVT)); in LowerFixedLengthVectorStoreToSVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9644 MVT TruncVT = MVT::getIntegerVT(EltSize); in SkipExtensionForVMULL() local
9653 return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops); in SkipExtensionForVMULL()
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