| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2653 MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, in decomposeSubvectorInsertExtractToSubRegs() argument
2660 unsigned SubRegClassID = getRegClassIDForVecVT(SubVecVT); in decomposeSubvectorInsertExtractToSubRegs()
2668 assert(SubVecVT.isScalableVector() && in decomposeSubvectorInsertExtractToSubRegs()
2670 assert(getLMUL(VecVT) == getLMUL(SubVecVT) && in decomposeSubvectorInsertExtractToSubRegs()
11400 MVT SubVecVT = SubVec.getSimpleValueType(); in lowerINSERT_SUBVECTOR() local
11415 if (SubVecVT.getVectorElementType() == MVT::i1) { in lowerINSERT_SUBVECTOR()
11417 SubVecVT.getVectorMinNumElements() >= 8) { in lowerINSERT_SUBVECTOR()
11420 SubVecVT.getVectorMinNumElements() % 8 == 0 && in lowerINSERT_SUBVECTOR()
11423 SubVecVT = in lowerINSERT_SUBVECTOR()
11424 MVT::getVectorVT(MVT::i8, SubVecVT.getVectorMinNumElements() / 8, in lowerINSERT_SUBVECTOR()
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| H A D | RISCVISelDAGToDAG.cpp | 2525 MVT SubVecVT = SubV.getSimpleValueType(); in Select() local
2528 MVT SubVecContainerVT = SubVecVT; in Select()
2530 if (SubVecVT.isFixedLengthVector()) { in Select()
2531 SubVecContainerVT = TLI.getContainerForFixedLengthVector(SubVecVT); in Select()
2534 Subtarget->expandVScale(SubVecVT.getSizeInBits()) in Select()
2536 assert(isPowerOf2_64(Subtarget->expandVScale(SubVecVT.getSizeInBits()) in Select()
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| H A D | RISCVISelLowering.h | 379 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
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| H A D | RISCVTargetTransformInfo.cpp | 1003 MVT SubVecVT = getTLI()->getValueType(DL, SubVecTy).getSimpleVT(); in getInterleavedMemoryOpCost() local
1004 Cost += Factor * TLI->getLMULCost(SubVecVT); in getInterleavedMemoryOpCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1671 EVT SubVecVT = SubVec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR() local
1673 unsigned SubElems = SubVecVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1687 if (VecVT.isScalableVector() == SubVecVT.isScalableVector() && in SplitVecRes_INSERT_SUBVECTOR()
1694 if (getTypeAction(SubVecVT) == TargetLowering::TypeWidenVector && in SplitVecRes_INSERT_SUBVECTOR()
1695 Vec.isUndef() && SubVecVT.getVectorElementType() == MVT::i1) { in SplitVecRes_INSERT_SUBVECTOR()
1718 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in SplitVecRes_INSERT_SUBVECTOR()
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| H A D | TargetLowering.cpp | 10641 EVT SubVecVT, in getVectorSubVecPointer() argument
10653 assert(SubVecVT.getVectorElementType() == EltVT && in getVectorSubVecPointer()
10656 SubVecVT.getVectorElementCount()); in getVectorSubVecPointer()
10659 if (SubVecVT.isScalableVector()) in getVectorSubVecPointer()
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| H A D | LegalizeIntegerTypes.cpp | 6058 EVT SubVecVT = SubVec.getValueType(); in PromoteIntRes_INSERT_SUBVECTOR() local
6061 SubVecVT.getVectorElementCount()); in PromoteIntRes_INSERT_SUBVECTOR()
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| H A D | DAGCombiner.cpp | 22990 EVT SubVecVT = SubVec.getValueType(); in combineInsertEltToShuffle() local
22992 unsigned NumSrcElts = SubVecVT.getVectorNumElements(); in combineInsertEltToShuffle()
22997 unsigned ExtendRatio = VT.getSizeInBits() / SubVecVT.getSizeInBits(); in combineInsertEltToShuffle()
23014 EVT SubVecEltVT = SubVecVT.getVectorElementType(); in combineInsertEltToShuffle()
23022 SmallVector<SDValue, 8> ConcatOps(ExtendRatio, DAG.getUNDEF(SubVecVT)); in combineInsertEltToShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 675 EVT SubVecVT = IsExtract ? getTLI()->getValueType(DL, RetTy) in getIntrinsicInstrCost() local
679 if (isUnpackedVectorVT(VecVT) || isUnpackedVectorVT(SubVecVT)) in getIntrinsicInstrCost()
683 getTLI()->getTypeConversion(C, SubVecVT); in getIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6610 MVT SubVecVT = MVT::getVectorVT(EltTy, SubVecNumElt); in lowerLaneOp() local
6614 Src0SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src0, in lowerLaneOp()
6619 Src1SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src1, in lowerLaneOp()
6623 Src2SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src2, in lowerLaneOp()
6628 ? createLaneOp(Src0SubVec, Src1SubVec, Src2, SubVecVT) in lowerLaneOp()
6629 : createLaneOp(Src0SubVec, Src1, Src2SubVec, SubVecVT)); in lowerLaneOp()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 5618 EVT SubVecVT, SDValue Index) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4590 MVT SubVecVT = SubVec.getSimpleValueType(); in insert1BitVector() local
4591 unsigned SubVecNumElems = SubVecVT.getVectorNumElements(); in insert1BitVector()
4593 IdxVal % SubVecVT.getSizeInBits() == 0 && in insert1BitVector()
4650 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVecVT, Vec, ZeroIdx); in insert1BitVector()
51364 EVT SubVecVT = SubVec.getValueType(); in combineScalarAndWithMaskSetcc() local
51367 if (!TLI.isTypeLegal(SubVecVT) || in combineScalarAndWithMaskSetcc()
51368 !C1->getAPIntValue().isMask(SubVecVT.getVectorNumElements())) in combineScalarAndWithMaskSetcc()
51393 DAG.getConstant(0, dl, SubVecVT)); in combineScalarAndWithMaskSetcc()
59238 MVT SubVecVT = SubVec.getSimpleValueType(); in combineINSERT_SUBVECTOR() local
59240 int SubVecNumElts = SubVecVT.getVectorNumElements(); in combineINSERT_SUBVECTOR()
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