Searched refs:SubLo (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 575 unsigned SubLo; in combine() local 580 SubLo = Hexagon::isub_lo; in combine() 584 SubLo = Hexagon::vsub_lo; in combine() 589 MCRegister DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
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| H A D | HexagonBitSimplify.cpp | 448 unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo); in parseRegSequence() local 450 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 451 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 456 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1635 unsigned SubLo = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_lo); in processBlock() local 1637 BitTracker::RegisterRef TL = { R, SubLo }; in processBlock() 1645 .addImm(SubLo) in processBlock() 1700 unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo); in propagateRegCopy() local 1702 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI); in propagateRegCopy() 1710 unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo); in propagateRegCopy() local [all …]
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| H A D | HexagonConstPropagation.cpp | 1950 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate() local 1952 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate() 1954 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate() 1957 bool LoIs1 = (Sub1 == SubLo); in evaluate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | BUFInstructions.td | 1850 defvar SubLo = !if(!eq(vt, i32), sub0, sub0_sub1); 1854 (REG_SEQUENCE DataRC, SrcRC:$data, SubLo, SrcRC:$cmp, SubHi), 1861 (EXTRACT_SUBREG OffsetResDag, SubLo), 1866 (REG_SEQUENCE DataRC, SrcRC:$data, SubLo, SrcRC:$cmp, SubHi), 1875 (EXTRACT_SUBREG IdxenResDag, SubLo), 1880 (REG_SEQUENCE DataRC, SrcRC:$data, SubLo, SrcRC:$cmp, SubHi), 1889 (EXTRACT_SUBREG OffenResDag, SubLo), 1894 (REG_SEQUENCE DataRC, SrcRC:$data, SubLo, SrcRC:$cmp, SubHi), 1903 (EXTRACT_SUBREG BothenResDag, SubLo),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 42750 if (SDValue SubLo = FindSubVector128(Imm & 0x0F)) { in combineTargetShuffle() local 42753 SubLo = DAG.getBitcast(SubVT, SubLo); in combineTargetShuffle() 42755 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, SubLo, SubHi); in combineTargetShuffle()
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