| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 250 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32, in tryInlineAsm() local
254 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 218 SDValue Sub0 = in selectInlineAsm() local
223 CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1)); in selectInlineAsm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 970 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectADD_SUB_I64() local
974 DL, MVT::i32, LHS, Sub0); in SelectADD_SUB_I64()
979 DL, MVT::i32, RHS, Sub0); in SelectADD_SUB_I64()
1012 Sub0, in SelectADD_SUB_I64()
1167 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32); in SelectMUL_LOHI() local
1169 MVT::i32, SDValue(Mad, 0), Sub0); in SelectMUL_LOHI()
1809 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectFlatOffsetImpl() local
1813 DL, MVT::i32, N0, Sub0); in SelectFlatOffsetImpl()
1832 SDValue(Add, 0), Sub0, SDValue(Addc, 0), Sub1}; in SelectFlatOffsetImpl()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 463 const MCInst *Sub0 = MI.getOperand(0).getInst(); in encodeSingleInstruction() local
467 unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI); in encodeSingleInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2238 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD() local
2241 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2521 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane() local
2524 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
5784 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm() local
5788 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7282 Register Sub0; in matchSimplifyNegMinMax() local
7283 auto NegPattern = m_all_of(m_Neg(m_DeferredReg(X)), m_Reg(Sub0)); in matchSimplifyNegMinMax()
7293 B.buildInstr(NewOpc, {DestReg}, {X, Sub0}); in matchSimplifyNegMinMax()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4002 SDValue Sub0 = N->getOperand(0); in foldRemainderIdiom() local
4008 DivRem.getResNo() == 0 && DivRem.getOperand(0) == Sub0 && in foldRemainderIdiom()
4033 Shl0.getResNo() == 0 && Shl0.getOperand(0) == Sub0) { in foldRemainderIdiom()
25472 SDValue Sub0 = getSubVectorSrc(Bop0, Index, SubVT); in narrowInsertExtractVectorBinOp() local
25478 if (!Sub0 || !Sub1) in narrowInsertExtractVectorBinOp()
25484 return DAG.getNode(BinOpcode, DL, SubVT, Sub0, Sub1, BinOp->getFlags()); in narrowInsertExtractVectorBinOp()
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