Searched refs:SignExt (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/clang/include/clang/CodeGen/ |
| H A D | CGFunctionInfo.h | 118 bool SignExt : 1; // isExtend() variable
141 SignExt(false), ZeroExt(false) {}
333 assert(isExtend() && (SignExt + ZeroExt <= 1) && "Invalid kind / flags!"); in isSignExt()
334 return SignExt; in isSignExt()
338 SignExt = SExt; in setSignExt()
342 assert(isExtend() && (SignExt + ZeroExt <= 1) && "Invalid kind / flags!"); in isZeroExt()
351 assert(isExtend() && (SignExt + ZeroExt <= 1) && "Invalid kind / flags!"); in isNoExt()
352 return !SignExt && !ZeroExt; in isNoExt()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | EmulateInstructionRISCV.cpp | 57 constexpr int32_t SignExt(uint32_t imm) { return int32_t(imm); } in SignExt() function
222 return rs1 + uint64_t(SignExt(inst.imm)); in LoadStoreAddr()
682 bool operator()(LUI inst) { return inst.rd.Write(m_emu, SignExt(inst.imm)); } in operator ()()
687 SignExt(inst.imm) + pc); in operator ()()
695 m_emu.WritePC(SignExt(inst.imm) + pc); in operator ()()
704 m_emu.WritePC((SignExt(inst.imm) + rs1) & in operator ()()
716 return m_emu.WritePC(SignExt(inst.imm) + pc); in operator ()()
743 m_emu, rs1 + int64_t(SignExt(inst.imm))); in operator ()()
751 m_emu, rs1 < int64_t(SignExt(inst.imm))); in operator ()()
759 m_emu, rs1 < uint64_t(SignExt(inst.imm))); in operator ()()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyIndVar.cpp | 1326 auto GuessNonIVOperand = [&](bool SignExt) { in cloneArithmeticIVUser() argument
1330 auto GetExtend = [this, SignExt](const SCEV *S, Type *Ty) { in cloneArithmeticIVUser()
1331 if (SignExt) in cloneArithmeticIVUser()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 545 bool SignExt = false; in tryShrinkShlLogicImm() local
548 SignExt = true; in tryShrinkShlLogicImm()
572 if (SignExt && ShAmt >= 32) in tryShrinkShlLogicImm()
584 unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI; in tryShrinkShlLogicImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 25365 SDValue SignExt = Curr; in LowerEXTEND_VECTOR_INREG() local
25386 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()
25394 SignExt = DAG.getVectorShuffle(MVT::v4i32, dl, SignExt, Sign, {0, 4, 1, 5}); in LowerEXTEND_VECTOR_INREG()
25395 SignExt = DAG.getBitcast(VT, SignExt); in LowerEXTEND_VECTOR_INREG()
25398 return SignExt; in LowerEXTEND_VECTOR_INREG()
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