Shift1 (reference) in projects: freebsd

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Searched refs:Shift1 (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A D	AggressiveInstCombine.cpp	`735 uint64_t Shift1 = 0, Shift2 = 0; in foldLoadsRecursive() local 737 Shift1 = ShAmt1->getZExtValue(); in foldLoadsRecursive() 755 if ((Shift2 - Shift1) != ShiftDiff \|\| (Offset2 - Offset1) != PrevSize) in foldLoadsRecursive()`
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A D	AMDGPUInstructionSelector.cpp	`737 bool Shift1 = mi_match( in selectG_BUILD_VECTOR() local 741 if (Shift0 && Shift1) { in selectG_BUILD_VECTOR() 745 } else if (Shift1) { in selectG_BUILD_VECTOR()`
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A D	InstructionSimplify.cpp	`2054 const APInt Shift1, Shift2; in simplifyAndCommutative() local 2055 if (match(Op0, m_Shl(m_Value(X), m_APInt(Shift1))) && in simplifyAndCommutative() 2059 Shift1->uge(*Shift2)) in simplifyAndCommutative()`
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	13943 SDValue Shift1 = in expandMul() 13946 DAG.getConstant(ScaleShift, DL, VT), Shift1); in expandMul() 13976 SDValue Shift1 = in expandMul() 13978 return DAG.getNode(ISD::ADD, DL, VT, Shift1, in expandMul() 13988 SDValue Shift1 = in expandMul() 13994 return DAG.getNode(ISD::SUB, DL, VT, Shift1, Mul359); in expandMul() 14004 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in expandMul() 14009 return DAG.getNode(ISD::SUB, DL, VT, Shift1, Shift2); in expandMul() 13940 SDValue Shift1 = expandMul() local 13973 SDValue Shift1 = expandMul() local 13985 SDValue Shift1 = expandMul() local 14001 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), expandMul() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A D	CombinerHelper.cpp	`1948 Register Shift1 = in applyShiftOfShiftedLogic() local 1965 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()`
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A D	PPCInstrInfo.td	`5131 def Shift1 { 5137 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5138 (AND Shift1.Left, MaskValues.Hi1));`
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A D	DAGCombiner.cpp	`7602 SDValue Shift1 = N1.getOperand(0); in matchBSwapHWordOrAndAnd() local 7603 if (Shift0.getOpcode() != ISD::SHL \|\| Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd() 7606 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1)); in matchBSwapHWordOrAndAnd() 7611 if (Shift0.getOperand(0) != Shift1.getOperand(0)) in matchBSwapHWordOrAndAnd()`
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86ISelLowering.cpp	`29569 SDValue Shift1 = getTargetVShiftByConstNode(X86OpcI, dl, VT, R, in LowerShift() local 29573 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift() 47697 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local 47701 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial() 48031 SDValue Shift1 = in combineMul() local 48037 NewMul = DAG.getNode(*Opc, DL, VT, Shift1, Shift2); in combineMul()`