| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 310 unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOpSubword() local
319 SLTu = Mips::SLTu_MM; in expandAtomicBinOpSubword()
331 SLTu = Mips::SLTu; in expandAtomicBinOpSubword()
494 unsigned SLTScratch4 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOpSubword()
717 unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOp() local
725 SLTu = Mips::SLTu_MM; in expandAtomicBinOp()
740 SLTu = Mips::SLTu; in expandAtomicBinOp()
755 SLTu = Mips::SLTu64; in expandAtomicBinOp()
895 unsigned SLTScratch2 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOp()
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| H A D | MipsCondMov.td | 199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
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| H A D | MipsInstructionSelector.cpp | 765 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp); in select()
768 Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS); in select()
771 Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS); in select()
775 Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS); in select()
778 Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS); in select()
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| H A D | MipsFastISel.cpp | 654 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
658 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
661 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
665 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
671 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
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| H A D | MipsInstrInfo.td | 2081 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>,
2759 (SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
2762 (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
3297 defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>,
3350 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>, ISA_MIPS1;
3351 defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
3352 defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1;
3353 defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
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| H A D | MipsScheduleI6400.td | 120 SELEQZ, SELEQZ64, SELNEZ, SELNEZ64, SLL, SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV,
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| H A D | Mips32r6InstrInfo.td | 1182 (SLTu ZERO, (ANDi (MFC1 (CLASS_S f32:$lhs)),
1186 (SLTu ZERO, (ANDi (MFC1_D64 (CLASS_D f64:$lhs)),
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| H A D | MipsScheduleP5600.td | 225 SEB, SEH, SLT, SLTu, SLL, SRA, SRL, XORi,
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| H A D | MipsScheduleGeneric.td | 50 SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV, SRL,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4156 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, in expandCondBranches()
4564 OpCode = Mips::SLTu; in expandSge()
4601 OpRegCode = Mips::SLTu; in expandSgeImm()
4657 OpCode = Mips::SLTu; in expandSgtImm()
4701 OpCode = Mips::SLTu; in expandSle()
4737 OpRegCode = Mips::SLTu; in expandSleImm()
4814 FinalOpcode = Mips::SLTu; in expandAliasImmediate()
5468 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSne()
5473 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); in expandSne()
5493 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI); in expandSneI()
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