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Searched refs:Rss (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td95 // Rss - 64-bit system registers.
96 class Rss<bits<7> num, string n, list<Register> subregs,
373 def SGP1_0 : Rss<0, "s1:0", [SGP0, SGP1], ["sgp1:0"]>, DwarfRegNum<[144]>;
374 def S3_2 : Rss<2, "s3:2", [STID, ELR]>, DwarfRegNum<[146]>;
375 def S5_4 : Rss<4, "s5:4", [BADVA0, BADVA1], ["badva1:0"]>,
377 def S7_6 : Rss<6, "s7:6", [SSR, CCR], ["ccr:ssr"]>, DwarfRegNum<[150]>;
378 def S9_8 : Rss<8, "s9:8", [HTID, BADVA]>, DwarfRegNum<[152]>;
379 def S11_10 : Rss<10, "s11:10", [IMASK, S11]>, DwarfRegNum<[154]>;
380 def S13_12 : Rss<12, "s13:12", [S12, S13]>, DwarfRegNum<[156]>;
381 def S15_14 : Rss<14, "s15:14", [S14, S15]>, DwarfRegNum<[158]>;
[all …]
H A DHexagonIntrinsicsV5.td24 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
28 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
32 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
36 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
61 //Rxx^=asr(Rss,Rt)
63 //Rxx^=asl(Rss,Rt)
65 //Rxx^=lsr(Rss,Rt)
67 //Rxx^=lsl(Rss,Rt)
154 // Rdd=vcnegh(Rss,Rt)
182 // Rxx+=vrcrotate(Rss,Rt,#u2)
[all …]
H A DHexagonPatterns.td1172 def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)),
1173 (A2_swiz (HiReg $Rss)))>;
1608 def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)),
1609 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)),
1610 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>;
1612 def: Pat<(v2i32 (mulhs V2I32:$Rss, V2I32:$Rtt)),
1613 (Combinew (M2_mpy_up (HiReg $Rss), (HiReg $Rtt)),
1614 (M2_mpy_up (LoReg $Rss), (LoReg $Rtt)))>;
1619 OutPatFrag<(ops node:$Rss, node:$Rtt),
1620 (Combinew (Mulhub4 (HiReg $Rss), (HiReg $Rtt)),
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/scudo/standalone/
H A Dlinux.cpp212 u64 Rss = 0; GetRSSFromBuffer() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1801 MCOperand &Rss = Inst.getOperand(1); in processInstruction() local
1809 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); in processInstruction()
1812 Rss.setReg(matchRegister(Reg1)); in processInstruction()
1818 TmpInst.addOperand(Rss); in processInstruction()
1885 MCOperand &Rss = Inst.getOperand(2); in processInstruction() local
1902 TmpInst.addOperand(Rss); in processInstruction()
1945 MCOperand &Rss = Inst.getOperand(1); in processInstruction() local
1953 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); in processInstruction()
1956 Rss.setReg(matchRegister(Reg1)); in processInstruction()
1962 TmpInst.addOperand(Rss); in processInstruction()