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Searched refs:RetVT (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRuntimeLibcallUtil.h33 LLVM_ABI Libcall getFPEXT(EVT OpVT, EVT RetVT);
37 LLVM_ABI Libcall getFPROUND(EVT OpVT, EVT RetVT);
41 LLVM_ABI Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
45 LLVM_ABI Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
49 LLVM_ABI Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
53 LLVM_ABI Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
57 LLVM_ABI Libcall getPOWI(EVT RetVT);
61 LLVM_ABI Libcall getPOW(EVT RetVT);
65 LLVM_ABI Libcall getLDEXP(EVT RetVT);
69 LLVM_ABI Libcall getFREXP(EVT RetVT);
[all …]
H A DFastISel.h351 virtual Register fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
355 virtual Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0);
359 virtual Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
365 virtual Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
378 virtual Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
383 virtual Register fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
439 Register fastEmitInst_extractsubreg(MVT RetVT, Register Op0, uint32_t Idx);
H A DTargetLowering.h4065 EVT RetVT, ArrayRef<SDValue> Ops,
4907 MakeLibCallOptions &setTypeListBeforeSoften(ArrayRef<EVT> OpsVT, EVT RetVT,
4910 RetVTBeforeSoften = RetVT;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp120 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { in getFPEXT() argument
122 if (RetVT == MVT::f32) in getFPEXT()
124 if (RetVT == MVT::f64) in getFPEXT()
126 if (RetVT == MVT::f80) in getFPEXT()
128 if (RetVT == MVT::f128) in getFPEXT()
131 if (RetVT == MVT::f64) in getFPEXT()
133 if (RetVT == MVT::f128) in getFPEXT()
135 if (RetVT == MVT::ppcf128) in getFPEXT()
138 if (RetVT == MVT::f128) in getFPEXT()
140 else if (RetVT == MVT::ppcf128) in getFPEXT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp194 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
199 Register emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
202 Register emitAddSub_rr(bool UseAdd, MVT RetVT, Register LHSReg,
205 Register emitAddSub_ri(bool UseAdd, MVT RetVT, Register LHSReg, uint64_t Imm,
207 Register emitAddSub_rs(bool UseAdd, MVT RetVT, Register LHSReg,
211 Register emitAddSub_rx(bool UseAdd, MVT RetVT, Register LHSReg,
219 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
220 bool emitICmp_ri(MVT RetVT, Register LHSReg, uint64_t Imm);
221 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
230 Register emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
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H A DAArch64TargetTransformInfo.cpp925 EVT RetVT = getTLI()->getValueType(DL, RetTy); in getIntrinsicInstrCost() local
927 if (!getTLI()->shouldExpandGetActiveLaneMask(RetVT, OpVT) && in getIntrinsicInstrCost()
928 !getTLI()->isTypeLegal(RetVT)) { in getIntrinsicInstrCost()
H A DAArch64ISelLowering.cpp26043 const EVT RetVT = N->getValueType(0); in performGatherLoadCombine() local
26044 assert(RetVT.isScalableVector() && in performGatherLoadCombine()
26050 if (RetVT.getSizeInBits().getKnownMinValue() > AArch64::SVEBitsPerBlock) in performGatherLoadCombine()
26065 RetVT.getScalarSizeInBits()); in performGatherLoadCombine()
26069 RetVT.getScalarSizeInBits()); in performGatherLoadCombine()
26092 RetVT.getScalarSizeInBits() / 8)) { in performGatherLoadCombine()
26118 EVT HwRetVt = getSVEContainerType(RetVT); in performGatherLoadCombine()
26123 SDValue OutVT = DAG.getValueType(RetVT); in performGatherLoadCombine()
26124 if (RetVT.isFloatingPoint()) in performGatherLoadCombine()
26135 if (RetVT.isInteger() && (RetVT != HwRetVt)) in performGatherLoadCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DFastISelEmitter.cpp510 MVT::SimpleValueType RetVT = MVT::isVoid; in collectPatterns() local
512 RetVT = InstPatNode.getSimpleType(0); in collectPatterns()
513 MVT::SimpleValueType VT = RetVT; in collectPatterns()
579 {Operands, OpcodeName, VT, RetVT, PredicateCheck}); in collectPatterns()
587 SimplePatterns[Operands][OpcodeName][VT][RetVT].emplace(Complexity, in collectPatterns()
687 for (const auto &[RetVT, PM] : RM) { in printFunctionDefinitions()
690 << getLegalCName(getEnumName(RetVT)) << "_"; in printFunctionDefinitions()
696 emitInstructionCode(OS, Operands, PM, getEnumName(RetVT)); in printFunctionDefinitions()
708 for (const auto &[RetVT, _] : RM) { in printFunctionDefinitions()
709 OS << " case " << getEnumName(RetVT) << ": return fastEmit_" in printFunctionDefinitions()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp179 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
1476 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) { in finishCall() argument
1487 if (RetVT != MVT::isVoid) { in finishCall()
1490 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS); in finishCall()
1500 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) in finishCall()
1506 if (RetVT == CopyVT) { in finishCall()
1512 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in finishCall()
1520 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) { in finishCall()
1560 MVT RetVT; in fastLowerCall() local
1562 RetVT = MVT::isVoid; in fastLowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp250 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2083 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs, in FinishCall() argument
2093 if (RetVT != MVT::isVoid) { in FinishCall()
2096 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg)); in FinishCall()
2099 if (RVLocs.size() == 2 && RetVT == MVT::f64) { in FinishCall()
2120 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) in FinishCall()
2271 MVT RetVT; in ARMEmitLibcall() local
2273 RetVT = MVT::isVoid; in ARMEmitLibcall()
2274 else if (!isTypeLegal(RetTy, RetVT)) in ARMEmitLibcall()
2278 if (RetVT != MVT::isVoid && RetVT != MVT::i32) { in ARMEmitLibcall()
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H A DARMISelLowering.cpp3341 auto RetVT = Outs[realRVLocIdx].ArgVT; in LowerReturn() local
3342 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) { in LowerReturn()
3347 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits()); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp110 bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I);
112 bool X86FastEmitSSESelect(MVT RetVT, const Instruction *I);
114 bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I);
236 MVT RetVT; in foldX86XALUIntrinsic() local
240 if (!isTypeLegal(RetTy, RetVT)) in foldX86XALUIntrinsic()
243 if (RetVT != MVT::i32 && RetVT != MVT::i64) in foldX86XALUIntrinsic()
2030 bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { in X86FastEmitCMoveSelect() argument
2036 if (RetVT < MVT::i16 || RetVT > MVT::i64) in X86FastEmitCMoveSelect()
2040 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
2156 bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) { in X86FastEmitSSESelect() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp195 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
240 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
289 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, in emitLogicalOp() argument
1282 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, in finishCall() argument
1286 if (RetVT != MVT::isVoid) { in finishCall()
1300 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) in finishCall()
1518 MVT RetVT; in fastLowerCall() local
1520 RetVT = MVT::isVoid; in fastLowerCall()
1521 else if (!isTypeSupported(CLI.RetTy, RetVT)) in fastLowerCall()
1589 return finishCall(CLI, RetVT, NumBytes); in fastLowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp1264 static RTLIB::Libcall findFPToIntLibcall(EVT SrcVT, EVT RetVT, EVT &Promoted, in findFPToIntLibcall() argument
1272 if (Promoted.bitsGE(RetVT)) in findFPToIntLibcall()
2516 EVT RetVT = N->getOperand(0).getValueType(); in ExpandFloatOp_LROUND() local
2518 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT, in ExpandFloatOp_LROUND()
2529 EVT RetVT = N->getOperand(0).getValueType(); in ExpandFloatOp_LLROUND() local
2531 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT, in ExpandFloatOp_LLROUND()
2542 EVT RetVT = N->getOperand(0).getValueType(); in ExpandFloatOp_LRINT() local
2544 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT, in ExpandFloatOp_LRINT()
2555 EVT RetVT = N->getOperand(0).getValueType(); in ExpandFloatOp_LLRINT() local
2557 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT, in ExpandFloatOp_LLRINT()
[all …]
H A DLegalizeDAG.cpp133 bool IsSigned, EVT RetVT);
2129 bool IsSigned, EVT RetVT) { in ExpandLibCall() argument
2140 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); in ExpandLibCall()
2206 EVT RetVT = Node->getValueType(0); in ExpandFPLibCall() local
2211 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT, in ExpandFPLibCall()
2369 EVT RetVT = Node->getValueType(0); in ExpandDivRemLibCall() local
2370 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); in ExpandDivRemLibCall()
2385 SDValue FIPtr = DAG.CreateStackTemporary(RetVT); in ExpandDivRemLibCall()
2408 DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo()); in ExpandDivRemLibCall()
4614 EVT RetVT = Node->getValueType(0); in ConvertNodeToLibcall() local
[all …]
H A DFastISel.cpp2178 Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, Register Op0, in fastEmitInst_extractsubreg() argument
2180 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
H A DTargetLowering.cpp154 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, in makeLibCall() argument
191 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); in makeLibCall()
418 EVT RetVT = getCmpLibcallReturnType(); in softenSetCCOperands() local
423 CallOptions.setTypeListBeforeSoften(OpsVT, RetVT, true); in softenSetCCOperands()
424 auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain); in softenSetCCOperands()
426 NewRHS = DAG.getConstant(0, dl, RetVT); in softenSetCCOperands()
436 assert(RetVT.isInteger()); in softenSetCCOperands()
437 CCCode = getSetCCInverse(CCCode, RetVT); in softenSetCCOperands()
454 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT); in softenSetCCOperands()
455 if (getBooleanContents(RetVT) == ZeroOrOneBooleanContent) { in softenSetCCOperands()
[all …]
H A DLegalizeVectorTypes.cpp7826 EVT RetVT = WidenEltVT; in findMemType() local
7832 return RetVT; in findMemType()
7848 RetVT = MemVT; in findMemType()
7869 if (RetVT.getFixedSizeInBits() < MemVTWidth || MemVT == WidenVT) in findMemType()
7879 return RetVT; in findMemType()
H A DLegalizeIntegerTypes.cpp3145 EVT RetVT = Node->getValueType(0); in ExpandAtomic() local
3157 return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node), in ExpandAtomic()
4251 EVT RetVT = N->getValueType(0); in ExpandIntRes_XROUND_XRINT() local
4255 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT, in ExpandIntRes_XROUND_XRINT()
H A DSelectionDAGBuilder.cpp6877 EVT RetVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitIntrinsicCall() local
6878 setValue(&I, DAG.getNode(Opcode, sdl, RetVT, in visitIntrinsicCall()
10975 EVT RetVT = OldRetTys[i]; in LowerCallTo() local
10977 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT); in LowerCallTo()
10978 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT); in LowerCallTo()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp1173 EVT RetVT = TLI.getValueType(DL, I->getType()); in selectBitCast() local
1174 if (!VT.isSimple() || !RetVT.isSimple()) in selectBitCast()
1181 if (VT == RetVT) { in selectBitCast()
1187 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), in selectBitCast()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h627 EVT RetVT, ArrayRef<SDValue> Ops, CallingConv::ID CallConv,
H A DSystemZISelLowering.cpp2457 SDValue Chain, SelectionDAG &DAG, const char *CalleeName, EVT RetVT, in makeExternalCall() argument
2475 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); in makeExternalCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp2750 EVT RetVT = Op.getValueType(); in lowerUINT_TO_FP() local
2751 RTLIB::Libcall LC = RTLIB::getUINTTOFP(OpVT, RetVT); in lowerUINT_TO_FP()
2753 CallOptions.setTypeListBeforeSoften(OpVT, RetVT, true); in lowerUINT_TO_FP()
2775 EVT RetVT = Op.getValueType(); in lowerSINT_TO_FP() local
2776 RTLIB::Libcall LC = RTLIB::getSINTTOFP(OpVT, RetVT); in lowerSINT_TO_FP()
2778 CallOptions.setTypeListBeforeSoften(OpVT, RetVT, true); in lowerSINT_TO_FP()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp10803 MVT RetVT = VT; in LowerINTRINSIC_WO_CHAIN() local
10805 RetVT = getContainerForFixedLengthVector(VT); in LowerINTRINSIC_WO_CHAIN()
10807 RetVT = MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits()), in LowerINTRINSIC_WO_CHAIN()
10810 SDValue NewNode = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, RetVT, Operands); in LowerINTRINSIC_WO_CHAIN()
10836 MVT RetVT = VT; in getVCIXISDNodeWCHAIN() local
10840 RetVT = MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits()), in getVCIXISDNodeWCHAIN()
10842 FloatVT = RetVT; in getVCIXISDNodeWCHAIN()
10845 RetVT = getContainerForFixedLengthVector(DAG.getTargetLoweringInfo(), RetVT, in getVCIXISDNodeWCHAIN()
10850 SDVTList VTs = DAG.getVTList({RetVT, MVT::Other}); in getVCIXISDNodeWCHAIN()

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