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Searched refs:RegClassID (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp116 unsigned RegClassID; in Select() local
123 RegClassID = R600::R600_Reg64RegClassID; in Select()
127 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
129 RegClassID = R600::R600_Reg128RegClassID; in Select()
134 SelectBuildVector(N, RegClassID); in Select()
H A DAMDGPUISelDAGToDAG.h88 void SelectBuildVector(SDNode *N, unsigned RegClassID);
H A DAMDGPUISelDAGToDAG.cpp437 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector() argument
442 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
486 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
676 unsigned RegClassID = in Select() local
678 SelectBuildVector(N, RegClassID); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TileConfig.cpp79 unsigned RegClassID = MRI->getRegClass(Reg)->getID(); in INITIALIZE_PASS_DEPENDENCY() local
80 if (RegClassID == X86::TILERegClassID) in INITIALIZE_PASS_DEPENDENCY()
82 if (RegClassID == X86::TILEPAIRRegClassID) in INITIALIZE_PASS_DEPENDENCY()
H A DX86FastPreTileConfig.cpp272 unsigned RegClassID = MRI->getRegClass(Reg)->getID(); in getTileDefNum() local
273 if (RegClassID == X86::TILERegClassID) in getTileDefNum()
275 if (RegClassID == X86::TILEPAIRRegClassID) in getTileDefNum()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h108 const char* getRegClassName(unsigned RegClassID) const;
111 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
H A DAMDGPUDisassembler.cpp157 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
1385 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
1387 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
1406 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
1408 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
1410 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1137 MCRegister GetSIDIForRegClass(unsigned RegClassID, bool IsSIReg);
1198 bool parseSEHRegisterNumber(unsigned RegClassID, MCRegister &RegNo);
1665 MCRegister X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, bool IsSIReg) { in GetSIDIForRegClass() argument
1666 switch (RegClassID) { in GetSIDIForRegClass()
1700 int RegClassID = -1; in VerifyAndAdjustOperands() local
1721 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1722 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1728 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1730 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1732 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp516 unsigned RegClassID = ChainBegin->getDesc().operands()[0].RegClass; in scavengeRegister() local
517 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
H A DAArch64RegisterInfo.td767 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
1012 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
1053 # RegClass # "RegClassID>";
1105 # RegClass # "RegClassID>";
1218 # RegClassSuffix # "RegClassID>";
1294 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
1432 # "AArch64::ZPR" # RegClassSuffix # "RegClassID" # ">";
1736 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
1877 # EltSize # ", AArch64::" # RC # "RegClassID>";
1904 # EltSize # ", AArch64::" # RC # "RegClassID>";
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H A DAArch64FrameLowering.cpp4728 auto ComputeScavengeableRegisters = [&](unsigned RegClassID) { in processFunctionBeforeFrameFinalized() argument
4729 BitVector Regs = TRI.getAllocatableSet(MF, TRI.getRegClass(RegClassID)); in processFunctionBeforeFrameFinalized()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp38 template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
338 template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
346 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg); in DecodeSimpleRegisterClass()
1652 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1659 MCRegister Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); in DecodeGPRSeqPairsClassRegisterClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp77 static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) { in isMemOperand() argument
80 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; in isMemOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1293 unsigned RegClassID; in convertVRToVRMx() local
1295 RegClassID = RISCV::VRM2RegClassID; in convertVRToVRMx()
1297 RegClassID = RISCV::VRM4RegClassID; in convertVRToVRMx()
1299 RegClassID = RISCV::VRM8RegClassID; in convertVRToVRMx()
1303 &RISCVMCRegisterClasses[RegClassID]); in convertVRToVRMx()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1427 template <unsigned RegClassID> bool isGPR64() const { in isGPR64()
1429 AArch64MCRegisterClasses[RegClassID].contains(getReg()); in isGPR64()
1432 template <unsigned RegClassID, int ExtWidth>
1437 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1875 template<unsigned Bits, unsigned RegClassID>
1878 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) in isMemImm7ShiftedOffset()