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Searched refs:PLLE_SS_CNTL (Results 1 – 4 of 4) sorted by relevance

/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c586 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
588 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
602 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
607 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
610 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
614 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
H A Dtegra124_car.h54 #define PLLE_SS_CNTL 0x068 macro
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c779 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
781 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
793 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
802 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
805 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
809 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
H A Dtegra210_car.h58 #define PLLE_SS_CNTL 0x068 macro