Home
last modified time | relevance | path

Searched refs:OutR (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp392 RegSubRegPair OutR(getRegSubRegPair(Op0)); in convertToPredForm() local
411 const TargetRegisterClass *RC = MRI->getRegClass(OutR.Reg); in convertToPredForm()
415 MRI->replaceRegWith(OutR.Reg, NewOutR); in convertToPredForm()
H A DHexagonBitSimplify.cpp2933 bool isShuffleOf(unsigned OutR, unsigned InpR) const;
3026 bool HexagonLoopRescheduling::isShuffleOf(unsigned OutR, unsigned InpR) const { in isShuffleOf() argument
3027 if (!BTP->has(OutR) || !BTP->has(InpR)) in isShuffleOf()
3029 const BitTracker::RegisterCell &OutC = BTP->lookup(OutR); in isShuffleOf()