| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 190 int64_t Offset0 = 0; in getHazardType() local
208 Ptr0 = GetPointerBaseWithConstantOffset(BaseVal0, Offset0, DL, true); in getHazardType()
211 return CheckOffsets(Offset0, Offset1); in getHazardType()
220 Offset0 = MF.getFrameInfo().getObjectOffset(FS0->getFrameIndex()); in getHazardType()
222 return CheckOffsets(Offset0, Offset1); in getHazardType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.h | 125 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
135 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
137 bool SelectDS128Bit8ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
139 bool SelectDSReadWrite2(SDValue Ptr, SDValue &Base, SDValue &Offset0,
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| H A D | AMDGPUISelDAGToDAG.cpp | 1266 bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0, in isDSOffset2Legal() argument
1269 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
1271 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
1360 SDValue &Offset0, in SelectDS64Bit4ByteAligned() argument
1362 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4); in SelectDS64Bit4ByteAligned()
1366 SDValue &Offset0, in SelectDS128Bit8ByteAligned() argument
1368 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 8); in SelectDS128Bit8ByteAligned()
1372 SDValue &Offset0, SDValue &Offset1, in SelectDSReadWrite2() argument
1386 Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i32); in SelectDSReadWrite2()
1422 Offset0 = in SelectDSReadWrite2()
[all …]
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| H A D | AMDGPUInstructionSelector.h | 266 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
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| H A D | SIInstrInfo.h | 246 bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
264 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
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| H A D | SIInstrInfo.cpp | 237 int64_t &Offset0, in areLoadsFromSameBasePtr() argument
277 Offset0 = Load0->getConstantOperandVal(Offset0Idx); in areLoadsFromSameBasePtr()
309 Offset0 = Load0Offset->getZExtValue(); in areLoadsFromSameBasePtr()
342 Offset0 = Off0->getAsZExtVal(); in areLoadsFromSameBasePtr()
403 unsigned Offset0 = Offset0Op->getImm() & 0xff; in getMemOperandsWithOffsetWidth() local
405 if (Offset0 + 1 != Offset1) in getMemOperandsWithOffsetWidth()
424 Offset = EltSize * Offset0; in getMemOperandsWithOffsetWidth()
612 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
614 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
620 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
[all …]
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| H A D | DSInstructions.td | 169 Offset0:$offset0, Offset1:$offset1, gds:$gds),
254 (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, Offset0:$offset0, Offset1:$offset1, gds:$gds),
330 (ins VGPR_32:$addr, Offset0:$offset0, Offset1:$offset1, gds:$gds),
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| H A D | AMDGPUInstructionSelector.cpp | 1802 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
1811 unsigned Offset = Offset0 | (Offset1 << 8); in selectDSOrderedIntrinsic()
5734 bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0, in isDSOffset2Legal() argument
5737 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
5739 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
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| H A D | SIInstrInfo.td | 1199 def Offset0 : NamedIntOperand<"offset0">;
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| H A D | SIISelLowering.cpp | 9474 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
9483 unsigned Offset = Offset0 | (Offset1 << 8); in LowerINTRINSIC_W_CHAIN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 394 int64_t Offset0; in apply() local
396 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0); in apply()
416 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| H A D | HexagonISelLoweringHVX.cpp | 2233 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); in LowerHvxMaskedOp() local
2237 {Mask, Base, Offset0, Value, Chain}, DAG); in LowerHvxMaskedOp()
2264 {MaskU.first, Base, Offset0, ValueU.first, Chain}, DAG); in LowerHvxMaskedOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 1273 APInt Offset0(IndexWidth, 0); in ConstantFoldCompareInstOperands() local
1276 DL, Offset0, /*AllowNonInbounds=*/IsEqPred, in ConstantFoldCompareInstOperands()
1287 ICmpInst::compare(Offset0, Offset1, in ConstantFoldCompareInstOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 19630 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
19639 APInt CNV = Offset0; in CombineToPreIndexedLoadStore()
21961 int64_t Offset0 = LoadNodes[0].OffsetFromBase; in tryStoreMergeOfLoads() local
21964 if (Offset0 - Offset1 == ElementSizeBytes && in tryStoreMergeOfLoads()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6413 bool Offset0 = false, Offset1 = false; in getFauxShuffleMask() local
6425 Offset0 = true; in getFauxShuffleMask()
6450 if (Offset0 || Offset1) { in getFauxShuffleMask()
6452 if ((Offset0 && isInRange(M, 0, NumElts)) || in getFauxShuffleMask()
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