Home
last modified time | relevance | path

Searched refs:NoRegister (Results 1 – 25 of 116) sorted by relevance

12345

/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyReplacePhysRegs.cpp76 for (unsigned PReg = WebAssembly::NoRegister + 1; in runOnMachineFunction()
84 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction()
88 if (VReg == WebAssembly::NoRegister) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegister.h52 static constexpr unsigned NoRegister = 0u; variable
75 assert(Val == NoRegister || isPhysicalRegister(Val)); in from()
81 constexpr bool isValid() const { return Reg != NoRegister; } in isValid()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp358 if (RegNum == AVR::NoRegister) { in parseRegisterName()
361 if (RegNum == AVR::NoRegister) { in parseRegisterName()
371 if (RegNum == AVR::NoRegister) in parseRegisterName()
378 int RegNum = AVR::NoRegister; in parseRegister()
392 if (RegNum == AVR::NoRegister && RestoreOnFailure) { in parseRegister()
406 if (RegNo == AVR::NoRegister) in tryParseRegisterOperand()
578 if (RegNo == AVR::NoRegister) in parseMemriOperand()
604 return Reg == AVR::NoRegister; in parseRegister()
613 if (Reg == AVR::NoRegister) in tryParseRegister()
765 if (RegNum != AVR::NoRegister) { in validateTargetOperandClass()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUResourceUsageAnalysis.cpp217 MCPhysReg HighestVGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
226 MCPhysReg HighestAGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
233 Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister in analyzeResourceUsage()
238 MCPhysReg HighestSGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
248 Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister in analyzeResourceUsage()
251 Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister in analyzeResourceUsage()
297 case AMDGPU::NoRegister: in analyzeResourceUsage()
H A DR600RegisterInfo.cpp66 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
74 return R600::NoRegister; in getFrameRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMakeCompressible.cpp239 return RegImmPair(RISCV::NoRegister, 0); in getRegImmPairPreventingCompression()
272 return RegImmPair(RISCV::NoRegister, 0); in getRegImmPairPreventingCompression()
314 return RISCV::NoRegister; in analyzeCompressibleUses()
328 return RISCV::NoRegister; in analyzeCompressibleUses()
H A DRISCVVectorPeephole.cpp181 if (MergeReg != RISCV::NoRegister && TRI->lookThruCopyLike(MergeReg, MRI) != in convertVMergeToVMv()
239 if (MI.getOperand(PassthruOpIdx).getReg() != RISCV::NoRegister) in convertToUnmasked()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h113 MIB.addReg(ARM::NoRegister);
121 MIB.addReg(ARM::NoRegister);
178 MIB.addReg(ARM::NoRegister);
H A DThumb1FrameLowering.cpp78 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
183 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
196 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
421 unsigned ScratchRegister = ARM::NoRegister; in emitPrologue()
520 NumBytes - ArgRegsSaveSize, ARM::NoRegister, in emitEpilogue()
541 unsigned ScratchRegister = ARM::NoRegister; in emitEpilogue()
557 assert(ScratchRegister != ARM::NoRegister && in emitEpilogue()
767 ArgRegsSaveSize + 4, ARM::NoRegister, in emitPopSpecialFixUp()
814 ARM::NoRegister, MachineInstr::FrameDestroy); in emitPopSpecialFixUp()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp135 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
136 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
138 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
686 if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister) in MorphToMISCReg()
815 if (RegNum == VE::NoRegister) { in parseRegisterName()
835 Reg = VE::NoRegister; in tryParseRegister()
841 if (Reg == VE::NoRegister) in tryParseRegister()
844 if (Reg != VE::NoRegister) { in tryParseRegister()
1358 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand()
1364 if (BaseReg != VE::NoRegister) in parseMEMAsOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DLVLGen.cpp57 return VE::NoRegister; in getVL()
78 if (Reg != VE::NoRegister) { in runOnMachineBasicBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp118 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
119 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
121 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
170 unsigned Reg = VE::NoRegister; in DecodeV64RegisterClass()
207 if (Reg == VE::NoRegister) in DecodeMISCRegisterClass()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegister.h111 assert(Reg == MCRegister::NoRegister || in asMCReg()
116 constexpr bool isValid() const { return Reg != MCRegister::NoRegister; } in isValid()
H A DLiveRegMatrix.h141 MCRegister PhysReg = MCRegister::NoRegister);
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp505 assert(Producer != Hexagon::NoRegister); in getSingleInstruction()
522 assert(Producer != Hexagon::NoRegister); in getSingleInstruction()
688 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); in DecodeCtrRegsRegisterClass()
689 if (CtrlRegDecoderTable[RegNo] == NoRegister) in DecodeCtrRegsRegisterClass()
716 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); in DecodeCtrRegs64RegisterClass()
717 if (CtrlReg64DecoderTable[RegNo] == NoRegister) in DecodeCtrRegs64RegisterClass()
815 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister) in DecodeSysRegsRegisterClass()
843 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister) in DecodeSysRegs64RegisterClass()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp320 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI())) in isRelevantAddressingMode()
326 if (!(Index.isReg() && Index.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
328 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
398 .addReg(X86::NoRegister) in buildCopy()
400 .addReg(X86::NoRegister) in buildCopy()
417 .addReg(X86::NoRegister) in buildCopy()
419 .addReg(X86::NoRegister) in buildCopy()
H A DX86ArgumentStackSlotRebase.cpp168 .addUse(X86::NoRegister) in runOnMachineFunction()
170 .addUse(X86::NoRegister) in runOnMachineFunction()
H A DX86WinFixupBufferSecurityCheck.cpp155 .addReg(X86::NoRegister) in CreateFailCheckSequence()
157 .addReg(X86::NoRegister); in CreateFailCheckSequence()
H A DX86LoadValueInjectionRetHardening.cpp82 if (ClobberReg != X86::NoRegister) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp151 if (Reg == AArch64::NoRegister) in getFrameHelperName()
207 assert(Reg1 != AArch64::NoRegister); in emitStore()
208 const bool IsPaired = Reg2 != AArch64::NoRegister; in emitStore()
248 assert(Reg1 != AArch64::NoRegister); in emitLoad()
249 const bool IsPaired = Reg2 != AArch64::NoRegister; in emitLoad()
H A DAArch64SLSHardening.cpp322 Register Xm = Kind.HasXmOperand ? ParseRegName(XmStr) : AArch64::NoRegister; in parseThunkName()
370 if (Xm != AArch64::NoRegister) { in populateThunk()
431 Kind.HasXmOperand ? BLR.getOperand(1).getReg() : AArch64::NoRegister; in convertBLRToBL()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp37 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
94 unsigned PredReg = Hexagon::NoRegister; in init()
136 unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister; in init()
453 if (ProducerPredInfo.Register != Hexagon::NoRegister && in checkNewValues()
573 (ProducerPredicate.Register == Hexagon::NoRegister || in registerProducer()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsBaseInfo.h145 return Mips::NoRegister; in getMSARegFromFReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp268 if (MO.getReg() == RISCV::NoRegister) in printRegReg()
305 if (MO.getReg() == RISCV::NoRegister) in printVMaskReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTLSDynamicCall.cpp95 Register InReg = PPC::NoRegister; in processBlock()
277 assert(InReg != PPC::NoRegister && "Operand must be a register"); in processBlock()

12345