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Searched refs:NextReg (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp2015 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local
2021 TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
2026 .addReg(NextReg) in emitAlignedDPRCS2Spills()
2029 NextReg += 4; in emitAlignedDPRCS2Spills()
2035 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
2040 TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
2045 .addReg(NextReg) in emitAlignedDPRCS2Spills()
2048 NextReg += 4; in emitAlignedDPRCS2Spills()
2055 TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QPRRegClass); in emitAlignedDPRCS2Spills()
2062 NextReg += 2; in emitAlignedDPRCS2Spills()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVAsmPrinter.cpp649 unsigned NextReg = RISCV::X28; in LowerKCFI_CHECK() local
656 while (!isRegAvailable(NextReg)) in LowerKCFI_CHECK()
657 ++NextReg; in LowerKCFI_CHECK()
658 Reg = NextReg++; in LowerKCFI_CHECK()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp1474 unsigned NextReg = SrcReg; in getSrcVReg() local
1477 NextReg = getIncomingRegForBlock(Inst, BB1); in getSrcVReg()
1482 NextReg = Inst->getOperand(1).getReg(); in getSrcVReg()
1483 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg)) in getSrcVReg()
1485 SrcReg = NextReg; in getSrcVReg()
H A DPPCISelLowering.cpp6904 unsigned NextReg = State.getFirstUnallocated(GPRs); in CC_AIX() local
6905 while (NextReg != GPRs.size() && in CC_AIX()
6906 !isGPRShadowAligned(GPRs[NextReg], ObjAlign)) { in CC_AIX()
6913 NextReg = State.getFirstUnallocated(GPRs); in CC_AIX()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp3304 MCRegister NextReg = CSI[i + RegInc].getReg(); in computeCalleeSaveRegisterPairs() local
3308 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
3309 !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows, in computeCalleeSaveRegisterPairs()
3312 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
3315 if (AArch64::FPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
3316 !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI, in computeCalleeSaveRegisterPairs()
3318 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
3321 if (AArch64::FPR128RegClass.contains(NextReg)) in computeCalleeSaveRegisterPairs()
3322 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
3328 ((RPI.Reg1 - AArch64::Z0) & 1) == 0 && (NextReg == RPI.Reg1 + 1)) { in computeCalleeSaveRegisterPairs()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1484 Register NextReg = MI->getOperand(1).getReg(); in getTestBitReg() local
1486 if (!NextReg.isValid() || !MRI.hasOneNonDBGUse(NextReg)) in getTestBitReg()
1490 Reg = NextReg; in getTestBitReg()
1538 Register NextReg; in getTestBitReg() local
1546 NextReg = TestReg; in getTestBitReg()
1552 NextReg = TestReg; in getTestBitReg()
1559 NextReg = TestReg; in getTestBitReg()
1567 NextReg = TestReg; in getTestBitReg()
1582 NextReg = TestReg; in getTestBitReg()
1587 if (!NextReg.isValid()) in getTestBitReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3095 MCRegister NextReg; in ParseRegList() local
3099 if (!ParseAMDGPURegister(NextRegKind, NextReg, in ParseRegList()
3112 if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc)) in ParseRegList()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp6155 MCRegister NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg()); in ConvertXWPOperands() local
6156 Inst.addOperand(MCOperand::createReg(NextReg)); in ConvertXWPOperands()