| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 147 BinaryOperator *NewShift = BinaryOperator::Create(ShiftOpcode, X, NewShAmt); in reassociateShiftAmtsOfTwoSameDirectionShifts() local
154 NewShift->setHasNoUnsignedWrap(Sh0->hasNoUnsignedWrap() && in reassociateShiftAmtsOfTwoSameDirectionShifts()
156 NewShift->setHasNoSignedWrap(Sh0->hasNoSignedWrap() && in reassociateShiftAmtsOfTwoSameDirectionShifts()
159 NewShift->setIsExact(Sh0->isExact() && Sh1->isExact()); in reassociateShiftAmtsOfTwoSameDirectionShifts()
163 Instruction *Ret = NewShift; in reassociateShiftAmtsOfTwoSameDirectionShifts()
165 Builder.Insert(NewShift); in reassociateShiftAmtsOfTwoSameDirectionShifts()
166 Ret = CastInst::Create(Instruction::Trunc, NewShift, Sh0->getType()); in reassociateShiftAmtsOfTwoSameDirectionShifts()
334 auto *NewShift = BinaryOperator::Create(OuterShift->getOpcode(), X, in dropRedundantMaskingOfLeftShiftInput() local
337 return NewShift; in dropRedundantMaskingOfLeftShiftInput()
339 Builder.Insert(NewShift); in dropRedundantMaskingOfLeftShiftInput()
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| H A D | InstCombineCompares.cpp | 1767 Value *NewShift = in foldICmpAndShift() local
1772 Value *NewAnd = Builder.CreateAnd(Shift->getOperand(0), NewShift); in foldICmpAndShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4137 SDValue NewShift = in performShlCombine() local
4149 DAG.ExtractVectorElements(NewShift, HiOps, 0, NElts); in performShlCombine()
4155 Vec = DAG.getBuildVector(ConcatType, SL, {Zero, NewShift}); in performShlCombine()
4238 SDValue NewShift = in performSraCombine() local
4249 DAG.ExtractVectorElements(NewShift, LoOps, 0, NElts); in performSraCombine()
4256 Vec = DAG.getBuildVector(ConcatType, SL, {NewShift, HiShift}); in performSraCombine()
4346 SDValue NewShift = in performSrlCombine() local
4355 DAG.ExtractVectorElements(NewShift, LoOps, 0, NElts); in performSrlCombine()
4360 Vec = DAG.getBuildVector(ConcatType, SL, {NewShift, Zero}); in performSrlCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2193 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); in foldMaskedShiftToScaledMask() local
2202 insertDAGNode(DAG, N, NewShift); in foldMaskedShiftToScaledMask()
2203 DAG.ReplaceAllUsesWith(N, NewShift); in foldMaskedShiftToScaledMask()
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| H A D | X86ISelLowering.cpp | 44488 SDValue NewShift = TLO.DAG.getNode( in SimplifyDemandedBitsForTargetNode() local
44491 return TLO.CombineTo(Op, NewShift); in SimplifyDemandedBitsForTargetNode()
50062 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1); in combineShiftRightLogical() local
50063 return DAG.getNode(ISD::AND, DL, VT, NewShift, NewMask); in combineShiftRightLogical()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2729 Register NewShift = in applyCombineTruncOfShift() local
2735 replaceRegWith(MRI, Dst, NewShift); in applyCombineTruncOfShift()
2737 Builder.buildTrunc(Dst, NewShift); in applyCombineTruncOfShift()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 2780 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit() local
2782 return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC); in foldAddSubOfSignBit()
7290 SDValue NewShift = DAG.getNode(ShiftOpcode, DL, VT, LogicX, Y); in foldLogicOfShifts() local
7291 return DAG.getNode(LogicOpcode, DL, VT, NewShift, Z); in foldLogicOfShifts()
10206 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant() local
10208 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
11038 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
11040 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift); in visitSRL()
11047 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
11052 SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask); in visitSRL()
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| H A D | TargetLowering.cpp | 1927 SDValue NewShift = TLO.DAG.getNode(ISD::SHL, dl, HalfVT, NewOp, in SimplifyDemandedBits() local
1930 TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, NewShift); in SimplifyDemandedBits()
2035 SDValue NewShift = in SimplifyDemandedBits() local
2038 Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, NewShift)); in SimplifyDemandedBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 17556 SDValue NewShift = DAG.getNode(NewOpcode, DL, N->getVTList(), Op0, Op1, in PerformLongShiftCombine() local
17558 DAG.ReplaceAllUsesWith(N, NewShift.getNode()); in PerformLongShiftCombine()
17559 return NewShift; in PerformLongShiftCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 26720 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, X, C2); in performSHLCombine() local
26721 return DAG.getNode(ISD::AND, DL, VT, NewShift, NewRHS); in performSHLCombine()
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