Searched refs:MinVT (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 1011 EVT MinVT = getRegisterType(Context, ReturnMVT); in getTypeForExtReturn() local
1012 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4999 EVT MinVT = getRegisterType(MVT::i32); in getTypeForExtReturn() local
5000 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4214 EVT MinVT = getRegisterType(Cond ? MVT::i64 : MVT::i32); in getTypeForExtReturn() local
4215 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 14773 EVT MinVT = N0.getValueType(); in visitZERO_EXTEND() local
14778 unsigned MidBits = MinVT.getScalarSizeInBits(); in visitZERO_EXTEND()
14811 Op = DAG.getZeroExtendInReg(Op, DL, MinVT); in visitZERO_EXTEND()
14823 SDValue And = DAG.getZeroExtendInReg(Op, DL, MinVT); in visitZERO_EXTEND()
25333 EVT MinVT = SVT; in visitCONCAT_VECTORS() local
25341 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT; in visitCONCAT_VECTORS()
25352 Opnds.append(NumElts, DAG.getUNDEF(MinVT)); in visitCONCAT_VECTORS()
25361 DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinVT, Op.getOperand(i))); in visitCONCAT_VECTORS()
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| H A D | TargetLowering.cpp | 4812 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); in SimplifySetCC() local
4813 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
4815 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); in SimplifySetCC()
4820 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT); in SimplifySetCC()
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