Searched refs:MaxVGPRs (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.h | 209 << " SGPRs, " << Target.RP.getArchVGPRNum() << '/' << Target.MaxVGPRs 210 << " ArchVGPRs, " << Target.RP.getAGPRNum() << '/' << Target.MaxVGPRs 218 << 2 * Target.MaxVGPRs << " VGPRs (combined target)"; 231 unsigned MaxVGPRs; variable 243 return RP.getArchVGPRNum() + RP.getAGPRNum() <= 2 * MaxVGPRs; in satisifiesVGPRBanksTarget() 252 return NumVGPRs > MaxVGPRs || !satisfiesUnifiedTarget() || in isVGPRBankSaveBeneficial() 256 void setRegLimits(unsigned MaxSGPRs, unsigned MaxVGPRs,
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| H A D | GCNRegPressure.cpp | 120 unsigned MaxVGPRs = ST.getMaxNumVGPRs(MF); in less() local 140 VGPRForSGPRSpills - MaxVGPRs), in less() 144 OtherVGPRForSGPRSpills - MaxVGPRs), in less() 158 : (getAGPRNum() - MaxVGPRs)), in less() 162 : (O.getAGPRNum() - MaxVGPRs)), in less() 183 std::max(static_cast<int>(getVGPRNum(ST.hasGFX90AInsts()) - MaxVGPRs), in less() 188 static_cast<int>(O.getVGPRNum(ST.hasGFX90AInsts()) - MaxVGPRs), in less() 398 MaxVGPRs = std::min(ST.getAddressableNumArchVGPRs(), NumVGPRs); in setRegLimits() 421 if (RP.getVGPRNum(false) > MaxVGPRs && in satisfied()
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| H A D | SIFormMemoryClauses.cpp | 52 unsigned MaxVGPRs; member in __anon72ebc0cc0111::SIFormMemoryClausesImpl 214 MaxPressure.getVGPRNum(ST->hasGFX90AInsts()) <= MaxVGPRs / 2 && in checkPressure() 274 MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count(); in run()
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| H A D | AMDGPUPromoteAlloca.cpp | 99 unsigned MaxVGPRs; member in __anon98b3e5030111::AMDGPUPromoteAllocaImpl 183 unsigned MaxVGPRs = ST.getMaxNumVGPRs( in getMaxVGPRs() local 192 MaxVGPRs = std::min(MaxVGPRs, 32u); in getMaxVGPRs() 193 return MaxVGPRs; in getMaxVGPRs() 310 MaxVGPRs = getMaxVGPRs(CurrentLocalMemUsage, TM, F); in run() 315 : (MaxVGPRs * 32)) / in run()
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| H A D | GCNSchedStrategy.cpp | 1327 unsigned MaxVGPRs = ST.getMaxNumVGPRs(MF); in checkScheduling() local 1330 unsigned MaxArchVGPRs = std::min(MaxVGPRs, ST.getAddressableNumArchVGPRs()); in checkScheduling() 1333 if (PressureAfter.getVGPRNum(ST.hasGFX90AInsts()) > MaxVGPRs || in checkScheduling()
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| H A D | SIInstrInfo.cpp | 713 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass, in indirectCopyToAGPR() local 730 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) in indirectCopyToAGPR()
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