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Searched refs:MachineInstr (Results 1 – 25 of 918) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h39 class MachineInstr; variable
53 MachineInstr *MI;
77 MachineInstr *Logic;
78 MachineInstr *Shift2;
164 void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const;
180 bool tryCombineCopy(MachineInstr &MI) const;
181 bool matchCombineCopy(MachineInstr &MI) const;
182 void applyCombineCopy(MachineInstr &MI) const;
186 bool isPredecessor(const MachineInstr &DefMI,
187 const MachineInstr &UseMI) const;
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H A DLegalizerHelper.h39 class MachineInstr; variable
96 LLVM_ABI LegalizeResult legalizeInstrStep(MachineInstr &MI,
100 LLVM_ABI LegalizeResult libcall(MachineInstr &MI,
105 LLVM_ABI LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx,
111 LLVM_ABI LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx,
115 LLVM_ABI LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
119 LLVM_ABI LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
123 LLVM_ABI LegalizeResult fewerElementsVector(MachineInstr &MI,
128 LLVM_ABI LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
142 LLVM_ABI void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
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H A DGenericMachineInstrs.h28 class GenericMachineInstr : public MachineInstr {
40 static bool classof(const MachineInstr *MI) { in classof()
77 static bool classof(const MachineInstr *MI) { in classof()
89 static bool classof(const MachineInstr *MI) { in classof()
119 static bool classof(const MachineInstr *MI) { in classof()
127 static bool classof(const MachineInstr *MI) { in classof()
136 static bool classof(const MachineInstr *MI) { in classof()
151 static bool classof(const MachineInstr *MI) { in classof()
159 static bool classof(const MachineInstr *MI) { in classof()
179 static bool classof(const MachineInstr *MI) { in classof()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h34 class MachineInstr; variable
57 Register isLoadFromStackSlot(const MachineInstr &MI,
65 Register isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
188 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
197 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
205 bool expandPostRAPseudo(MachineInstr &MI) const override;
209 const MachineInstr &LdSt,
224 bool isPredicated(const MachineInstr &MI) const override;
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H A DHexagonVLIWPacketizer.h23 class MachineInstr; variable
29 std::vector<MachineInstr *> OldPacketMIs;
54 std::vector<MachineInstr*> IgnoreDepMIs;
89 bool ignorePseudoInstruction(const MachineInstr &MI,
94 bool isSoloInstruction(const MachineInstr &MI) override;
105 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
108 bool shouldAddToPacket(const MachineInstr &MI) override;
119 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
121 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
124 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.h25 class MachineInstr; variable
34 typedef function_ref<bool(const MachineInstr &)> IsHazardFn;
43 MachineInstr *CurrCycleInstr;
44 std::list<MachineInstr*> EmittedInstrs;
63 void addClauseInst(const MachineInstr &MI);
67 unsigned getMFMAPipelineWaitStates(const MachineInstr &MI) const;
75 void runOnInstruction(MachineInstr *MI);
81 int checkSoftClauseHazards(MachineInstr *SMEM);
82 int checkSMRDHazards(MachineInstr *SMRD);
83 int checkVMEMHazards(MachineInstr* VMEM);
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H A DAMDGPUInstructionSelector.h39 class MachineInstr; variable
58 bool select(MachineInstr &I) override;
74 bool isInstrUniform(const MachineInstr &MI) const;
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectCOPY_SCC_VCC(MachineInstr &I) const;
91 bool selectCOPY_VCC_SCC(MachineInstr &I) const;
92 bool selectReadAnyLane(MachineInstr &I) const;
93 bool selectPHI(MachineInstr &I) const;
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H A DAMDGPULegalizerInfo.h37 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
58 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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H A DSIInstrInfo.h54 void insert(MachineInstr *MI);
56 MachineInstr *top() const { in top()
73 bool isDeferred(MachineInstr *MI);
75 SetVector<MachineInstr *> &getDeferredList() { return DeferredList; } in getDeferredList()
79 SetVector<MachineInstr *> InstrList;
82 SetVector<MachineInstr *> DeferredList;
103 using SetVectorType = SmallSetVector<MachineInstr *, 32>;
121 void swapOperands(MachineInstr &Inst) const;
124 moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,
127 void lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,
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H A DR600InstrInfo.h35 class MachineInstr; variable
45 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
93 bool canBeConsideredALU(const MachineInstr &MI) const;
96 bool isTransOnly(const MachineInstr &MI) const;
98 bool isVectorOnly(const MachineInstr &MI) const;
102 bool usesVertexCache(const MachineInstr &MI) const;
104 bool usesTextureCache(const MachineInstr &MI) const;
107 bool usesAddressRegister(MachineInstr &MI) const;
108 bool definesAddressRegister(MachineInstr &MI) const;
109 bool readsLDSSrcReg(const MachineInstr &MI) const;
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h143 virtual bool isGlobalMemoryObject(const MachineInstr *MI) const;
150 bool isTriviallyReMaterializable(const MachineInstr &MI) const { in isTriviallyReMaterializable()
163 virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, in isSafeToSink()
170 virtual bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const { in shouldBreakCriticalEdgeToSink()
181 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const;
198 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
227 bool isFrameInstr(const MachineInstr &I) const { in isFrameInstr()
233 bool isFrameSetup(const MachineInstr &I) const { in isFrameSetup()
245 int64_t getFrameSize(const MachineInstr &I) const { in getFrameSize()
254 int64_t getFrameTotalSize(const MachineInstr &I) const { in getFrameTotalSize()
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H A DReachingDefAnalysis.h34 class MachineInstr; variable
141 DenseMap<MachineInstr *, int> InstIds;
155 using InstSet = SmallPtrSetImpl<MachineInstr*>;
190 int getReachingDef(MachineInstr *MI, Register Reg) const;
193 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, Register Reg) const;
197 bool isReachingDefLiveOut(MachineInstr *MI, Register Reg) const;
201 MachineInstr *getLocalLiveOutMIDef(MachineBasicBlock *MBB,
206 MachineInstr *getUniqueReachingMIDef(MachineInstr *MI, Register Reg) const;
210 MachineInstr *getMIOperand(MachineInstr *MI, unsigned Idx) const;
214 MachineInstr *getMIOperand(MachineInstr *MI, MachineOperand &MO) const;
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H A DModuloSchedule.h75 class MachineInstr; variable
88 std::vector<MachineInstr *> ScheduledInstrs;
91 DenseMap<MachineInstr *, int> Cycle;
94 DenseMap<MachineInstr *, int> Stage;
108 std::vector<MachineInstr *> ScheduledInstrs, in ModuloSchedule()
109 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
110 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule()
135 int getStage(MachineInstr *MI) { in getStage()
141 int getCycle(MachineInstr *MI) { in getCycle()
147 void setStage(MachineInstr *MI, int MIStage) { in setStage()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h39 AC_EVEX_2_LEGACY = MachineInstr::TAsmComments,
60 CondCode getCondFromMI(const MachineInstr &MI);
63 CondCode getCondFromBranch(const MachineInstr &MI);
66 CondCode getCondFromSETCC(const MachineInstr &MI);
69 CondCode getCondFromCMov(const MachineInstr &MI);
72 CondCode getCondFromCFCMov(const MachineInstr &MI);
75 CondCode getCondFromCCMP(const MachineInstr &MI);
106 bool isX87Instruction(MachineInstr &MI);
112 int getFirstAddrOperandIdx(const MachineInstr &MI);
115 const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo);
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H A DX86AsmPrinter.h106 void LowerSTACKMAP(const MachineInstr &MI);
107 void LowerPATCHPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
108 void LowerSTATEPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
109 void LowerFAULTING_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
110 void LowerPATCHABLE_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
112 void LowerTlsAddr(X86MCInstLower &MCInstLowering, const MachineInstr &MI);
115 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
117 void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL);
118 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
119 void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h69 Register isLoadFromStackSlot(const MachineInstr &MI,
71 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
73 Register isStoreToStackSlot(const MachineInstr &MI,
75 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
78 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
80 bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override { in shouldBreakCriticalEdgeToSink()
98 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
104 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
107 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
117 MachineInstr::MIFlag Flag = MachineInstr::NoFlags,
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.h36 getInstrMapping(const MachineInstr &MI) const override;
48 void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const;
123 SmallVector<MachineInstr *, 2> DefUses;
124 SmallVector<MachineInstr *, 2> UseDefs;
134 MachineInstr *skipCopiesOutgoing(MachineInstr *MI) const;
141 MachineInstr *skipCopiesIncoming(MachineInstr *MI) const;
144 AmbiguousRegDefUseContainer(const MachineInstr *MI);
145 SmallVectorImpl<MachineInstr *> &getDefUses() { return DefUses; } in getDefUses()
146 SmallVectorImpl<MachineInstr *> &getUseDefs() { return UseDefs; } in getUseDefs()
154 DenseMap<const MachineInstr *, SmallVector<const MachineInstr *, 2>>
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H A DMipsInstrInfo.h35 class MachineInstr; variable
85 SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
94 bool SafeAfterMflo(const MachineInstr &MI) const;
97 bool SafeInForbiddenSlot(const MachineInstr &MI) const;
100 bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
101 const MachineInstr &FPUMI) const;
104 bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot,
105 const MachineInstr &LoadMI) const;
107 bool IsMfloOrMfhi(const MachineInstr &MI) const;
110 bool HasForbiddenSlot(const MachineInstr &MI) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h291 SmallVectorImpl<MachineInstr *> &NewMIs) const;
295 SmallVectorImpl<MachineInstr *> &NewMIs) const;
299 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
300 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
303 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
307 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
309 MachineInstr &DefMI) const;
312 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
313 unsigned ConstantOpNo, MachineInstr &DefMI,
320 MachineInstr *getForwardingDefMI(MachineInstr &MI,
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h191 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
193 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
195 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
197 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
199 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
201 void expandLoadStackGuard(MachineInstr *MI) const;
223 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
231 Register isLoadFromStackSlot(const MachineInstr &MI,
233 Register isStoreToStackSlot(const MachineInstr &MI,
235 Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h188 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
190 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
192 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
196 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
197 const MachineInstr &MIb) const override;
199 Register isLoadFromStackSlot(const MachineInstr &MI,
201 Register isStoreToStackSlot(const MachineInstr &MI,
205 static bool isGPRZero(const MachineInstr &MI);
208 static bool isGPRCopy(const MachineInstr &MI);
211 static bool isFPRCopy(const MachineInstr &MI);
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.h30 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
34 MachineInstr &MI) const override;
37 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
39 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
42 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeSmallCMGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeBitfieldExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeICMP(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeFunnelShift(MachineInstr &MI, MachineRegisterInfo &MRI,
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchMergeBaseOffset.cpp37 bool detectFoldable(MachineInstr &Hi20, MachineInstr *&Lo12,
38 MachineInstr *&Lo20, MachineInstr *&Hi12,
39 MachineInstr *&Last);
40 bool detectFoldable(MachineInstr &Hi20, MachineInstr *&Add,
41 MachineInstr *&Lo12);
43 bool detectAndFoldOffset(MachineInstr &Hi20, MachineInstr &Lo12,
44 MachineInstr *&Lo20, MachineInstr *&Hi12,
45 MachineInstr *&Last);
46 void foldOffset(MachineInstr &Hi20, MachineInstr &Lo12, MachineInstr *&Lo20,
47 MachineInstr *&Hi12, MachineInstr *&Last, MachineInstr &Tail,
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp77 MachineInstr *tryToCombine(MachineInstr &Ldst);
80 bool noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
81 const MachineInstr *Ldst);
85 bool canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
95 MachineInstr *canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
96 SmallVectorImpl<MachineInstr *> *Uses);
100 bool canFixPastUses(const ArrayRef<MachineInstr *> &Uses,
105 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
134 static bool isAddConstantOp(const MachineInstr &MI, int64_t &Amount) { in isAddConstantOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h66 const MachineInstr &MI, unsigned DefIdx,
79 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
95 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
106 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
113 isCopyInstrImpl(const MachineInstr &MI) const override;
118 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
159 bool isPredicated(const MachineInstr &MI) const override;
163 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
167 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { in getPredicate()
173 bool PredicateInstruction(MachineInstr &MI,
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