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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h41 MachineRegisterInfo &MRI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
61 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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H A DAMDGPURegisterBankInfo.cpp102 MachineRegisterInfo &MRI; member in __anon7ca9607e0111::ApplyRegBankMapping
109 : B(B), RBI(RBI_), MRI(MRI_), NewBank(RB) { in ApplyRegBankMapping()
131 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
134 assert(MRI.getType(SrcReg) == LLT::scalar(1)); in applyBank()
135 assert(MRI.getType(DstReg) == S32); in applyBank()
145 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
146 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
150 assert(!MRI.getRegClassOrRegBank(DstReg)); in applyBank()
151 MRI.setRegBank(DstReg, *NewBank); in applyBank()
158 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
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H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI,
90 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
100 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI,
106 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
111 const MachineRegisterInfo &MRI,
116 const MachineRegisterInfo &MRI,
121 const MachineRegisterInfo &MRI,
139 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
145 const MachineInstr &MI, const MachineRegisterInfo &MRI) cons
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H A DAMDGPURegBankLegalize.cpp84 MachineRegisterInfo &MRI) { in getRules() argument
91 It->second = std::make_unique<RegBankLegalizeRules>(ST, MRI); in getRules()
93 It->second->refreshRefs(ST, MRI); in getRules()
99 MachineRegisterInfo &MRI; member in AMDGPURegBankLegalizeCombiner
113 : B(B), MRI(*B.getMRI()), TRI(TRI), in AMDGPURegBankLegalizeCombiner()
119 const RegisterBank *RB = MRI.getRegBankOrNull(Reg); in isLaneMask()
123 const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg); in isLaneMask()
124 return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1); in isLaneMask()
129 if (Optional0 && isTriviallyDead(*Optional0, MRI)) in cleanUpAfterCombine()
134 MachineInstr *MatchMI = MRI.getVRegDef(Src); in tryMatch()
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H A DAMDGPUCombinerHelper.cpp78 const MachineRegisterInfo &MRI) { in opMustUseVOP3Encoding() argument
80 MRI.getType(MI.getOperand(0).getReg()).getScalarSizeInBits() == 64; in opMustUseVOP3Encoding()
124 static bool allUsesHaveSourceMods(MachineInstr &MI, MachineRegisterInfo &MRI, in allUsesHaveSourceMods() argument
133 for (const MachineInstr &Use : MRI.use_nodbg_instructions(Dst)) { in allUsesHaveSourceMods()
137 if (!opMustUseVOP3Encoding(Use, MRI)) { in allUsesHaveSourceMods()
163 MachineRegisterInfo &MRI) { in isConstantCostlierToNegate() argument
165 if (mi_match(Reg, MRI, m_GFCstOrSplat(FPValReg))) { in isConstantCostlierToNegate()
202 MatchInfo = MRI.getVRegDef(Src); in matchFoldableFneg()
208 if (MRI.hasOneNonDBGUse(Src)) { in matchFoldableFneg()
209 if (allUsesHaveSourceMods(MI, MRI, 0)) in matchFoldableFneg()
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H A DAMDGPUInstructionSelector.cpp64 MRI = &MF.getRegInfo(); in setupMF()
78 const MachineRegisterInfo &MRI) const { in isVCC()
83 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); in isVCC()
87 const LLT Ty = MRI.getType(Reg); in isVCC()
91 return MRI.getVRegDef(Reg)->getOpcode() != AMDGPU::G_TRUNC && in isVCC()
109 if (MRI->getType(Dst.getReg()) == LLT::scalar(1)) in constrainCopyLikeIntrin()
113 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in constrainCopyLikeIntrin()
115 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in constrainCopyLikeIntrin()
119 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
120 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp42 MachineRegisterInfo &MRI) { in IsRegInClass()
44 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
52 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
53 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
56 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
57 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
60 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
61 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
64 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
65 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h96 LLVM_ABI Register constrainRegToClass(MachineRegisterInfo &MRI,
111 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
127 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
148 MachineRegisterInfo &MRI);
153 const MachineRegisterInfo &MRI);
181 getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI);
185 getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI);
189 const MachineRegisterInfo &MRI);
202 const MachineRegisterInfo &MRI,
208 Register VReg, const MachineRegisterInfo &MRI,
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H A DMIPatternMatch.h28 [[nodiscard]] bool mi_match(Reg R, const MachineRegisterInfo &MRI, in mi_match() argument
30 return P.match(MRI, R); in mi_match()
34 [[nodiscard]] bool mi_match(MachineInstr &MI, const MachineRegisterInfo &MRI, in mi_match() argument
36 return P.match(MRI, &MI); in mi_match()
41 const MachineRegisterInfo &MRI, Pattern &&P) { in mi_match() argument
42 return P.match(MRI, &MI); in mi_match()
50 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
51 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); in match()
64 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
65 return MRI.hasOneNonDBGUse(Reg) && SubPat.match(MRI, Reg); in match()
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H A DLegalizationArtifactCombiner.h37 MachineRegisterInfo &MRI; variable
54 LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
57 : Builder(B), MRI(MRI), LI(LI), VT(VT) {} in Builder()
72 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineAnyExt()
74 if (MRI.getType(DstReg) == MRI.getType(TruncSrc)) in tryCombineAnyExt()
75 replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs, in tryCombineAnyExt()
80 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt()
87 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
98 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt()
100 const LLT DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp46 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass() argument
50 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
51 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
58 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
69 auto *OldRegClass = MRI.getRegClassOrNull(Reg); in constrainOperandRegClass()
70 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
95 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) { in constrainOperandRegClass()
98 MachineInstr *RegDef = MRI.getVRegDef(Reg); in constrainOperandRegClass()
101 Observer->changingAllUsesOfReg(MRI, Reg); in constrainOperandRegClass()
110 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
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H A DCombinerHelperVectorOps.cpp40 LLT DstTy = MRI.getType(Dst); in matchExtractVectorElement()
41 LLT VectorTy = MRI.getType(Vector); in matchExtractVectorElement()
73 getIConstantVRegValWithLookThrough(Index, MRI); in matchExtractVectorElement()
93 MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); in matchExtractVectorElementWithDifferentIndices()
115 getIConstantVRegValWithLookThrough(Index, MRI); in matchExtractVectorElementWithDifferentIndices()
126 getOpcodeDef<GInsertVectorElement>(Vector, MRI); in matchExtractVectorElementWithDifferentIndices()
133 getIConstantVRegValWithLookThrough(Insert->getIndexReg(), MRI); in matchExtractVectorElementWithDifferentIndices()
166 LLT VectorTy = MRI.getType(Vector); in matchExtractVectorElementWithBuildVector()
170 if (!MRI.hasOneNonDBGUse(Build->getReg(0)) || in matchExtractVectorElementWithBuildVector()
174 APInt Index = getIConstantFromReg(Extract->getIndexReg(), MRI); in matchExtractVectorElementWithBuildVector()
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H A DCombinerHelper.cpp62 : Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer), VT(VT), in CombinerHelper()
95 auto &MRI = *MIB.getMRI(); in buildLogBase2() local
96 LLT Ty = MRI.getType(V); in buildLogBase2()
181 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, in replaceRegWith() argument
183 Observer.changingAllUsesOfReg(MRI, FromReg); in replaceRegWith()
185 if (MRI.constrainRegAttrs(ToReg, FromReg)) in replaceRegWith()
186 MRI.replaceRegWith(FromReg, ToReg); in replaceRegWith()
193 void CombinerHelper::replaceRegOpWith(MachineRegisterInfo &MRI, in replaceRegOpWith() argument
214 return RBI->getRegBank(Reg, MRI, *TRI); in getRegBank()
220 MRI.setRegBank(Reg, *RegBank); in setRegBank()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp66 MachineRegisterInfo *MRI; member in __anon09bd49dc0111::AArch64AdvSIMDScalar
103 const MachineRegisterInfo *MRI) { in isGPR64() argument
107 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
112 const MachineRegisterInfo *MRI) { in isFPR64() argument
114 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
116 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
126 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
143 MRI) && in getSrcFromCopy()
144 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
147 MRI) && in getSrcFromCopy()
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H A DAArch64Combine.td17 [{ return matchFConstantToConstant(*${root}, MRI); }]),
24 … [{ return matchICmpRedundantTrunc(*${root}, MRI, Helper.getValueTracking(), ${matchinfo}); }]),
25 (apply [{ applyICmpRedundantTrunc(*${root}, MRI, B, Observer, ${matchinfo}); }])>;
32 [{ return matchFoldGlobalOffset(*${root}, MRI, ${matchinfo}); }]),
33 (apply [{ applyFoldGlobalOffset(*${root}, MRI, B, Observer, ${matchinfo});}])
42 [{ return matchExtAddvToUdotAddv(*${root}, MRI, STI, ${matchinfo}); }]),
43 (apply [{ applyExtAddvToUdotAddv(*${root}, MRI, B, Observer, STI, ${matchinfo}); }])
51 [{ return matchExtUaddvToUaddlv(*${root}, MRI, ${matchinfo}); }]),
52 (apply [{ applyExtUaddvToUaddlv(*${root}, MRI, B, Observer, ${matchinfo}); }])
60 …[{ return matchPushAddSubExt(*${root}, MRI, ${dst}.getReg(), ${src1}.getReg(), ${src2}.getReg()); …
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp80 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
82 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
84 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
86 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
88 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
90 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
92 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
94 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
96 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
98 bool selectUAddSub(MachineInstr &I, MachineRegisterInfo &MRI,
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H A DX86RegisterBankInfo.cpp48 static bool isFPIntrinsic(const MachineRegisterInfo &MRI, in isFPIntrinsic() argument
69 const MachineRegisterInfo &MRI, in hasFPConstraints() argument
73 if (Op == TargetOpcode::G_INTRINSIC && isFPIntrinsic(MRI, MI)) in hasFPConstraints()
87 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
102 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints()
107 const MachineRegisterInfo &MRI, in onlyUsesFP() argument
123 return hasFPConstraints(MI, MRI, TRI, Depth); in onlyUsesFP()
127 const MachineRegisterInfo &MRI, in onlyDefinesFP() argument
138 return hasFPConstraints(MI, MRI, TRI, Depth); in onlyDefinesFP()
198 const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP, in getInstrPartialMappingIdxs() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp153 bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI, in matchREV() argument
159 LLT Ty = MRI.getType(Dst); in matchREV()
189 bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI, in matchTRN() argument
195 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchTRN()
210 bool matchUZP(MachineInstr &MI, MachineRegisterInfo &MRI, in matchUZP() argument
216 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchUZP()
226 bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI, in matchZip() argument
232 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchZip()
244 MachineRegisterInfo &MRI, in matchDupFromInsertVectorElt() argument
265 MI.getOperand(1).getReg(), MRI); in matchDupFromInsertVectorElt()
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H A DAArch64InstructionSelector.cpp114 bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI);
118 MachineRegisterInfo &MRI);
120 bool convertPtrAddToAdd(MachineInstr &I, MachineRegisterInfo &MRI);
123 MachineRegisterInfo &MRI) const;
125 MachineRegisterInfo &MRI) const;
141 MachineRegisterInfo &MRI);
143 bool selectVectorAshrLshr(MachineInstr &I, MachineRegisterInfo &MRI);
144 bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI);
157 MachineRegisterInfo &MRI) const;
177 MachineRegisterInfo &MRI);
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H A DAArch64PreLegalizerCombiner.cpp49 bool matchFConstantToConstant(MachineInstr &MI, MachineRegisterInfo &MRI) { in matchFConstantToConstant() argument
52 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits(); in matchFConstantToConstant()
59 return all_of(MRI.use_nodbg_instructions(DstReg), in matchFConstantToConstant()
75 bool matchICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, in matchICmpRedundantTrunc() argument
84 LLT LHSTy = MRI.getType(LHS); in matchICmpRedundantTrunc()
91 if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) || in matchICmpRedundantTrunc()
92 !mi_match(RHS, MRI, m_SpecificICst(0))) in matchICmpRedundantTrunc()
95 LLT WideTy = MRI.getType(WideReg); in matchICmpRedundantTrunc()
104 void applyICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, in applyICmpRedundantTrunc() argument
109 LLT WideTy = MRI.getType(WideReg); in applyICmpRedundantTrunc()
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H A DAArch64PostLegalizerCombiner.cpp67 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd() argument
71 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchExtractVecEltPairwiseAdd()
73 auto Cst = getIConstantVRegValWithLookThrough(Src2, MRI); in matchExtractVecEltPairwiseAdd()
79 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI); in matchExtractVecEltPairwiseAdd()
91 getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI); in matchExtractVecEltPairwiseAdd()
92 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd()
94 Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI); in matchExtractVecEltPairwiseAdd()
95 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd()
100 Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) { in matchExtractVecEltPairwiseAdd()
110 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyExtractVecEltPairwiseAdd() argument
[all …]
H A DAArch64RegisterBankInfo.cpp258 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings() local
264 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
285 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
325 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
363 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyMappingImpl() local
378 MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID)); in applyMappingImpl()
384 assert(MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() < 32 && in applyMappingImpl()
389 auto ConstMI = MRI.getVRegDef(MI.getOperand(1).getReg()); in applyMappingImpl()
398 MRI.setRegBank(ConstReg, getRegBank(AArch64::GPRRegBankID)); in applyMappingImpl()
412 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getSameKindOfOperandsMapping() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp135 const MachineInstr &MI, const MachineRegisterInfo &MRI, in hasFPConstraints() argument
145 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == &RISCV::FPRBRegBank; in hasFPConstraints()
149 const MachineRegisterInfo &MRI, in onlyUsesFP() argument
163 return hasFPConstraints(MI, MRI, TRI); in onlyUsesFP()
167 const MachineRegisterInfo &MRI, in onlyDefinesFP() argument
177 return hasFPConstraints(MI, MRI, TRI); in onlyDefinesFP()
181 Register Def, const MachineRegisterInfo &MRI, in anyUseOnlyUseFP() argument
184 MRI.use_nodbg_instructions(Def), in anyUseOnlyUseFP()
185 [&](const MachineInstr &UseMI) { return onlyUsesFP(UseMI, MRI, TRI); }); in anyUseOnlyUseFP()
218 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp63 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
66 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
69 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
71 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
73 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
130 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr() argument
140 llvm::make_early_inc_range(MRI->use_operands(Op0.getReg()))) { in checkADDrr()
142 if (!MRI->getUniqueVRegDef(MO.getReg())) in checkADDrr()
178 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift() argument
192 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate() argument
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