| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 64 case ISD::MLOAD: in getVVPOpcode()
205 case ISD::MLOAD: in getMaskPos()
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| H A D | VEISelLowering.cpp | 344 for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE}) in initVPUActions()
1926 case ISD::MLOAD: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 141 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
181 setOperationAction(ISD::MLOAD, P, Custom); in initializeHVXLowering()
226 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
294 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
391 setOperationAction(ISD::MLOAD, BoolW, Custom); in initializeHVXLowering()
2215 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
2217 if (Opc == ISD::MLOAD) { in LowerHvxMaskedOp()
3021 uint64_t MemSize = (MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE) in SplitHvxMemOp()
3045 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
3052 if (MemOpc == ISD::MLOAD) { in SplitHvxMemOp()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1401 MLOAD, enumerator
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| H A D | SelectionDAGNodes.h | 1561 case ISD::MLOAD:
2827 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2830 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2846 return N->getOpcode() == ISD::MLOAD ||
2859 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2874 return N->getOpcode() == ISD::MLOAD;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 453 case ISD::MLOAD: return "masked_load"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 89 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N)); in PromoteIntegerResult()
2002 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N), in PromoteIntegerOperand()
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| H A D | SelectionDAG.cpp | 885 case ISD::MLOAD: { in AddNodeIDCustom()
3958 case ISD::MLOAD: { in computeKnownBits()
10188 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops); in getMaskedLoad()
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| H A D | LegalizeVectorTypes.cpp | 1158 case ISD::MLOAD: in SplitVectorResult()
4718 case ISD::MLOAD: in WidenVectorResult()
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| H A D | DAGCombiner.cpp | 2026 case ISD::MLOAD: return visitMLOAD(N); in visit()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1452 case ISD::MLOAD: in SelectT2AddrModeImm7Offset()
4011 case ISD::MLOAD: in Select()
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| H A D | ARMISelLowering.cpp | 281 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
355 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
10719 case ISD::MLOAD: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 806 def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1533 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1636 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1679 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1759 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
2316 setOperationAction(ISD::MLOAD, VT, Default); in addTypeForFixedLengthSVE()
7461 case ISD::MLOAD: in LowerOperation()
22410 return OC == ISD::LOAD || OC == ISD::MLOAD || in isCheapToExtend()
23041 if (N->getOperand(0).getOpcode() == ISD::MLOAD && in performUnpackCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 920 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1098 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1175 setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE, in RISCVTargetLowering()
1345 {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom); in RISCVTargetLowering()
1435 setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE, in RISCVTargetLowering()
8034 case ISD::MLOAD: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1654 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
1884 setOperationAction(ISD::MLOAD, VT, Custom); in X86TargetLowering()
2057 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
2064 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
2221 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2669 ISD::MLOAD, in X86TargetLowering()
33722 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG); in LowerOperation()
60534 case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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