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Searched refs:MI1 (Results 1 – 25 of 29) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp292 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
319 Info.MI1 = nullptr; in handleUse()
361 OpInfo.MI1 = &MI; in handleMiddleInst()
363 } else if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
366 OpInfo.MI1 = &MI; in handleMiddleInst()
375 if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
378 OpInfo.MI1 = &MI; in handleMiddleInst()
383 OpInfo.MI1 = &MI; in handleMiddleInst()
446 if (!areInstructionsConsecutive(Info.MI1, Info.MI0)) in handleADRP()
449 << '\t' << MI << '\t' << *Info.MI1 << '\t' in handleADRP()
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H A DAArch64MachineScheduler.cpp36 static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1, in mayOverlapWrite() argument
39 const MachineOperand &Base1 = AArch64InstrInfo::getLdStBaseOp(MI1); in mayOverlapWrite()
46 int StoreSize1 = AArch64InstrInfo::getMemScale(MI1); in mayOverlapWrite()
50 Off1 = AArch64InstrInfo::hasUnscaledLdStOffset(MI1.getOpcode()) in mayOverlapWrite()
51 ? AArch64InstrInfo::getLdStOffsetOp(MI1).getImm() in mayOverlapWrite()
52 : AArch64InstrInfo::getLdStOffsetOp(MI1).getImm() * StoreSize1; in mayOverlapWrite()
54 const MachineInstr &MI = (Off0 < Off1) ? MI0 : MI1; in mayOverlapWrite()
H A DSMEPeepholeOpt.cpp57 static bool isMatchingStartStopPair(const MachineInstr *MI1, in isMatchingStartStopPair() argument
61 if (MI1->getOperand(0).getImm() != MI2->getOperand(0).getImm()) in isMatchingStartStopPair()
65 if (MI1->getOperand(1).getImm() == MI2->getOperand(1).getImm()) in isMatchingStartStopPair()
69 if (isConditionalStartStop(MI1) != IsConditional) in isMatchingStartStopPair()
76 if (MI1->getOperand(2).getImm() != MI2->getOperand(2).getImm()) in isMatchingStartStopPair()
80 if (MI1->getOperand(4).getRegMask() != MI2->getOperand(4).getRegMask()) in isMatchingStartStopPair()
93 if (MI1->getOperand(3).isReg() && MI2->getOperand(3).isReg()) { in isMatchingStartStopPair()
94 Register Reg1 = MI1->getOperand(3).getReg(); in isMatchingStartStopPair()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
401 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) || in ReduceXWtoXWP()
469 (MI1->getOpcode() == Mips::LW_MM) || in ReduceXWtoXWP()
470 (MI1->getOpcode() == Mips::LW16_MM); in ReduceXWtoXWP()
472 if (!CheckXWPInstr(MI1, ReduceToLwp, Entry)) in ReduceXWtoXWP()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP()
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp487 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
525 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
526 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
535 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
536 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
539 << printMBBReference(*MI1->getParent()) << " " << *MI1); in hoistAndMergeSGPRInits()
540 MergedInstrs.insert(MI1); in hoistAndMergeSGPRInits()
546 auto *MBB = MDT.findNearestCommonDominator(MI1->getParent(), in hoistAndMergeSGPRInits()
554 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
557 << printMBBReference(*MI1->getParent()) << " " << *MI1 in hoistAndMergeSGPRInits()
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H A DGCNHazardRecognizer.cpp2333 const MachineInstr *MI1; in checkMAIHazards90A() local
2335 auto IsOverlappedMFMAFn = [Reg, &FullReg, &MI1, in checkMAIHazards90A()
2341 MI1 = &MI; in checkMAIHazards90A()
2355 unsigned Opc1 = MI1->getOpcode(); in checkMAIHazards90A()
2368 TSchedModel.computeInstrLatency(MI1) == 2) in checkMAIHazards90A()
2388 int NumPasses = TSchedModel.computeInstrLatency(MI1); in checkMAIHazards90A()
2390 if (TII.isXDL(*MI) && !TII.isXDL(*MI1)) in checkMAIHazards90A()
2394 TII.isXDL(*MI1) in checkMAIHazards90A()
2445 int NumPasses = TSchedModel.computeInstrLatency(MI1); in checkMAIHazards90A()
2449 TII.isXDL(*MI1) in checkMAIHazards90A()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp272 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias() argument
275 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
278 for (const MachineMemOperand *Op1 : MI1.memoperands()) in alias()
H A DTargetInstrInfo.cpp463 const MachineInstr &MI1, in produceSameValue() argument
465 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
918 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
921 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
926 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB); in hasReassociableOperands()
938 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
944 Commuted = !areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) && in hasReassociableSibling()
947 std::swap(MI1, MI2); in hasReassociableSibling()
957 return areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) && in hasReassociableSibling()
958 (isAssociativeAndCommutative(*MI1) || in hasReassociableSibling()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp263 MachineInstr &MI1 = *SU.getInstr(); in apply() local
265 bool IsStoreMI1 = MI1.mayStore(); in apply()
266 bool IsLoadMI1 = MI1.mayLoad(); in apply()
267 if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1)) in apply()
H A DHexagonVLIWPacketizer.cpp958 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements() argument
962 if (getPredicateSense(MI1, HII) == PK_Unknown || in arePredicatesComplements()
967 SUnit *SU = MIToSUnit[&MI1]; in arePredicatesComplements()
1015 unsigned PReg1 = getPredicatedRegister(MI1, HII); in arePredicatesComplements()
1020 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1021 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
H A DHexagonVLIWPacketizer.h144 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
H A DHexagonInstrInfo.h408 bool isToBeScheduledASAP(const MachineInstr &MI1,
420 bool addLatencyToSchedule(const MachineInstr &MI1,
H A DHexagonInstrInfo.cpp2690 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP() argument
2692 if (mayBeCurLoad(MI1)) { in isToBeScheduledASAP()
2694 Register DstReg = MI1.getOperand(0).getReg(); in isToBeScheduledASAP()
2702 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2703 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3067 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule() argument
3069 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
3070 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp276 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
397 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift() argument
401 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp); in getAddrDispShift()
H A DX86ISelLowering.h1860 MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp316 MachineInstr &MI1 = *MII; in ExpandFPMLxInstruction()
317 dbgs() << " " << MI1; in ExpandFPMLxInstruction()
H A DARMBaseInstrInfo.cpp1705 const MachineInstr &MI1, in produceSameValue() argument
1714 if (MI1.getOpcode() != Opcode) in produceSameValue()
1716 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1720 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue()
1750 if (MI1.getOpcode() != Opcode) in produceSameValue()
1752 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1756 Register Addr1 = MI1.getOperand(1).getReg(); in produceSameValue()
1773 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue()
1780 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
H A DARMBaseInstrInfo.h241 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDFAPacketizer.h215 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
H A DTargetInstrInfo.h619 const MachineInstr &MI1,
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLoadStoreOpt.h64 LLVM_ABI bool aliasIsKnownForLoadStore(const MachineInstr &MI1,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h332 bool areRVVInstsReassociable(const MachineInstr &MI1,
349 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
H A DRISCVInstrInfo.cpp2226 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableVectorSibling() local
2231 Commuted = !areRVVInstsReassociable(Inst, *MI1) && in hasReassociableVectorSibling()
2234 std::swap(MI1, MI2); in hasReassociableVectorSibling()
2236 return areRVVInstsReassociable(Inst, *MI1) && in hasReassociableVectorSibling()
2237 (isVectorAssociativeAndCommutative(*MI1) || in hasReassociableVectorSibling()
2238 isVectorAssociativeAndCommutative(*MI1, /* Invert */ true)) && in hasReassociableVectorSibling()
2239 hasReassociableOperands(*MI1, MBB) && in hasReassociableVectorSibling()
2240 MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg()); in hasReassociableVectorSibling()
2255 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
2258 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp101 bool GISelAddressing::aliasIsKnownForLoadStore(const MachineInstr &MI1, in aliasIsKnownForLoadStore() argument
105 auto *LdSt1 = dyn_cast<GLoadStore>(&MI1); in aliasIsKnownForLoadStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp1644 auto MI1 = in expandLSLW4Rd() local
1650 MI1->getOperand(3).setIsDead(); in expandLSLW4Rd()
1730 auto MI1 = in expandLSLW12Rd() local
1736 MI1->getOperand(3).setIsDead(); in expandLSLW12Rd()
1842 auto MI1 = in expandLSRW4Rd() local
1848 MI1->getOperand(3).setIsDead(); in expandLSRW4Rd()

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