Home
last modified time | relevance | path

Searched refs:MCRegister (Results 1 – 25 of 368) sorted by relevance

12345678910>>...15

/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h67 MCRegister getRegister(unsigned i) const { in getRegister()
74 bool contains(MCRegister Reg) const { in contains()
84 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains()
166 MCRegister RAReg; // Return address register
167 MCRegister PCReg; // Program counter register
191 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping
192 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping
195 ArrayRef<MCPhysReg> getCachedAliasesOf(MCRegister R) const;
242 iterator_range<MCSubRegIterator> subregs(MCRegister Reg) const;
246 iterator_range<MCSubRegIterator> subregs_inclusive(MCRegister Reg) const;
[all …]
H A DMCRegister.h33 class MCRegister {
34 friend hash_code hash_value(const MCRegister &);
38 constexpr MCRegister(unsigned Val = 0) : Reg(Val) {} in Reg()
69 static MCRegister from(unsigned Val) { in from()
71 return MCRegister(Val); in from()
79 constexpr bool operator==(const MCRegister &Other) const {
82 constexpr bool operator!=(const MCRegister &Other) const {
103 template <> struct DenseMapInfo<MCRegister> {
104 static inline MCRegister getEmptyKey() {
107 static inline MCRegister getTombstoneKey() {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h69 std::multimap<MCRegister, RegisterReference> RegRefs;
89 std::multimap<MCRegister, RegisterReference> &GetRegRefs() { in GetRegRefs()
95 unsigned GetGroup(MCRegister Reg);
100 unsigned Group, std::vector<MCRegister> &Regs,
101 std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
106 unsigned UnionGroups(MCRegister Reg1, MCRegister Reg2);
111 unsigned LeaveGroup(MCRegister Reg);
114 bool IsLive(MCRegister Reg);
170 void GetPassthruRegs(MachineInstr &MI, std::set<MCRegister> &PassthruRegs);
172 void HandleLastUse(MCRegister Reg, unsigned KillIdx, const char *tag,
[all …]
H A DRegAllocGreedy.h166 SmallVector<std::pair<const LiveInterval *, MCRegister>, 8>;
230 MCRegister PhysReg;
242 void reset(InterferenceCache &Cache, MCRegister Reg) { in reset()
295 MCRegister selectOrSplit(const LiveInterval &,
305 MCRegister selectOrSplitImpl(const LiveInterval &,
324 void calcGapWeights(MCRegister, SmallVectorImpl<float> &);
325 void evictInterference(const LiveInterval &, MCRegister,
327 bool mayRecolorAllInterferences(MCRegister PhysReg,
332 MCRegister tryAssign(const LiveInterval &, AllocationOrder &,
334 MCRegister tryEvict(const LiveInterval &, AllocationOrder &,
[all …]
H A DAggressiveAntiDepBreaker.cpp70 unsigned AggressiveAntiDepState::GetGroup(MCRegister Reg) { in GetGroup()
79 unsigned Group, std::vector<MCRegister> &Regs, in GetGroupRegs()
80 std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference> in GetGroupRegs() argument
88 unsigned AggressiveAntiDepState::UnionGroups(MCRegister Reg1, MCRegister Reg2) { in UnionGroups()
103 unsigned AggressiveAntiDepState::LeaveGroup(MCRegister Reg) { in LeaveGroup()
113 bool AggressiveAntiDepState::IsLive(MCRegister Reg) { in IsLive()
175 MCRegister AliasReg = *AI; in StartBlock()
192 std::set<MCRegister> PassthruRegs; in Observe()
241 MachineInstr &MI, std::set<MCRegister> &PassthruRegs) { in GetPassthruRegs()
290 void AggressiveAntiDepBreaker::HandleLastUse(MCRegister Reg, unsigned KillIdx, in HandleLastUse()
[all …]
H A DCriticalAntiDepBreaker.cpp70 MCRegister Reg = *AI; in StartBlock()
88 MCRegister Reg = *AI; in StartBlock()
333 MCRegister AliasReg = *AI; in ScanInstruction()
355 MCRegister NewReg) { in isNewRegClobberedByRefs()
394 MCRegister CriticalAntiDepBreaker::findSuitableFreeRegister( in findSuitableFreeRegister()
395 RegRefIter RegRefBegin, RegRefIter RegRefEnd, MCRegister AntiDepReg, in findSuitableFreeRegister()
396 MCRegister LastNewReg, const TargetRegisterClass *RC, in findSuitableFreeRegister()
399 for (MCRegister NewReg : Order) { in findSuitableFreeRegister()
433 return MCRegister(); in findSuitableFreeRegister()
520 std::vector<MCRegister> LastNewReg(TRI->getNumRegs(), MCRegister()); in BreakAntiDependencies()
[all …]
H A DCriticalAntiDepBreaker.h56 std::multimap<MCRegister, MachineOperand *> RegRefs;
59 std::multimap<MCRegister, MachineOperand *>::const_iterator;
100 MCRegister NewReg);
101 MCRegister
103 MCRegister AntiDepReg, MCRegister LastNewReg,
H A DRegAllocGreedy.cpp531 MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg, in tryAssign()
535 MCRegister PhysReg; in tryAssign()
554 MCRegister PhysHint = Hint.asMCReg(); in tryAssign()
565 return MCRegister(); in tryAssign()
581 MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters); in tryAssign()
590 MCRegister FromReg) const { in canReassign()
597 for (MCRegister Reg : in canReassign()
616 MCRegister PhysReg, in evictInterference()
656 bool RegAllocEvictionAdvisor::isUnusedCalleeSavedReg(MCRegister PhysReg) const { in isUnusedCalleeSavedReg()
657 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
[all …]
H A DLiveRegMatrix.cpp88 const LiveInterval &VRegInterval, MCRegister PhysReg, in foreachUnit()
111 void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) { in assign()
145 bool LiveRegMatrix::isPhysRegUsed(MCRegister PhysReg) const { in isPhysRegUsed()
154 MCRegister PhysReg) { in checkRegMaskInterference()
173 MCRegister PhysReg) { in checkRegUnitInterference()
195 MCRegister PhysReg) { in checkInterference()
219 MCRegister PhysReg) { in checkInterference()
250 MCRegister PhysReg) { in checkInterferenceLanes()
290 return MCRegister::NoRegister; in getOneVReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.h68 virtual void emitFrame(MCRegister StackReg, unsigned StackSize,
69 MCRegister ReturnReg);
128 void emitR(unsigned Opcode, MCRegister Reg0, SMLoc IDLoc,
132 void emitRX(unsigned Opcode, MCRegister Reg0, MCOperand Op1, SMLoc IDLoc,
134 void emitRI(unsigned Opcode, MCRegister Reg0, int32_t Imm, SMLoc IDLoc,
136 void emitRR(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, SMLoc IDLoc,
138 void emitRRX(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, MCOperand Op2,
140 void emitRRR(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
141 MCRegister Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI);
142 void emitRRRX(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
[all …]
H A DMipsTargetStreamer.cpp93 void MipsTargetStreamer::emitFrame(MCRegister StackReg, unsigned StackSize, in emitFrame()
94 MCRegister ReturnReg) {} in emitFrame()
185 void MipsTargetStreamer::emitR(unsigned Opcode, MCRegister Reg0, SMLoc IDLoc, in emitR()
194 void MipsTargetStreamer::emitRX(unsigned Opcode, MCRegister Reg0, MCOperand Op1, in emitRX()
204 void MipsTargetStreamer::emitRI(unsigned Opcode, MCRegister Reg0, int32_t Imm, in emitRI()
209 void MipsTargetStreamer::emitRR(unsigned Opcode, MCRegister Reg0, in emitRR()
210 MCRegister Reg1, SMLoc IDLoc, in emitRR()
225 void MipsTargetStreamer::emitRRX(unsigned Opcode, MCRegister Reg0, in emitRRX()
226 MCRegister Reg1, MCOperand Op2, SMLoc IDLoc, in emitRRX()
237 void MipsTargetStreamer::emitRRR(unsigned Opcode, MCRegister Reg0, in emitRRR()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp28 MCRegister Reg;
36 MCRegAliasIteratorImpl(MCRegister Reg, const MCRegisterInfo *MCRI) in MCRegAliasIteratorImpl()
52 MCRegister operator*() const { in operator *()
86 ArrayRef<MCPhysReg> MCRegisterInfo::getCachedAliasesOf(MCRegister R) const { in getCachedAliasesOf()
107 MCRegister
108 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
116 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg()
130 unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg, in getSubRegIndex()
131 MCRegister SubReg) const { in getSubRegIndex()
144 int64_t MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVModuleAnalysis.h130 using LocalToGlobalRegTable = std::map<Register, MCRegister>;
144 DenseMap<unsigned, MCRegister> ExtInstSetMap;
148 DenseMap<const Function *, MCRegister> FuncMap;
161 DenseMap<std::pair<const MachineFunction *, int>, MCRegister> BBNumToRegMap;
163 MCRegister getFuncReg(const Function *F) { in getFuncReg()
166 return FuncPtrRegPair == FuncMap.end() ? MCRegister() in getFuncReg()
169 MCRegister getExtInstSetReg(unsigned SetNum) { return ExtInstSetMap[SetNum]; } in getExtInstSetReg()
176 MCRegister AliasReg) { in setRegisterAlias()
179 MCRegister getRegisterAlias(const MachineFunction *MF, Register Reg) { in getRegisterAlias()
183 return MCRegister(); in getRegisterAlias()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegister.h24 constexpr Register(MCRegister Val) : Reg(Val.id()) {} in Register()
39 static_assert(FirstStackSlot >= MCRegister::LastPhysicalReg);
56 return MCRegister::isPhysicalRegister(Reg); in isPhysicalRegister()
97 constexpr operator MCRegister() const { return MCRegister(Reg); } in MCRegister() function
102 MCRegister asMCReg() const { in asMCReg()
104 return MCRegister(Reg); in asMCReg()
107 constexpr bool isValid() const { return Reg != MCRegister::NoRegister; } in isValid()
116 constexpr bool operator==(const MCRegister &Other) const {
119 constexpr bool operator!=(const MCRegister &Other) const {
H A DTargetRegisterInfo.h89 MCRegister getRegister(unsigned i) const { in getRegister()
349 const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg,
356 getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2,
363 const TargetRegisterClass *getMinimalPhysRegClassLLT(MCRegister Reg,
371 getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2,
396 bool isInAllocatableClass(MCRegister RegNo) const { in isInAllocatableClass()
471 bool hasRegUnit(MCRegister Reg, MCRegUnit RegUnit) const { in hasRegUnit()
582 explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const { in explainReservedReg()
589 MCRegister PhysReg) const { in isAsmClobberable()
595 MCRegister PhysReg) const { in isInlineAsmReadOnlyReg()
[all …]
H A DLiveRegMatrix.h109 MCRegister PhysReg);
116 bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg);
126 MCRegister PhysReg);
131 void assign(const LiveInterval &VirtReg, MCRegister PhysReg);
139 bool isPhysRegUsed(MCRegister PhysReg) const;
152 MCRegister PhysReg = MCRegister::NoRegister);
158 MCRegister PhysReg);
H A DCFIInstBuilder.h60 void buildDefCFA(MCRegister Reg, int64_t Offset) const { in buildDefCFA()
65 void buildDefCFARegister(MCRegister Reg) const { in buildDefCFARegister()
78 void buildOffset(MCRegister Reg, int64_t Offset) const { in buildOffset()
91 void buildRegister(MCRegister Reg1, MCRegister Reg2) const { in buildRegister()
101 void buildRestore(MCRegister Reg) const { in buildRestore()
106 void buildUndefined(MCRegister Reg) const { in buildUndefined()
111 void buildSameValue(MCRegister Reg) const { in buildSameValue()
H A DCallingConvLower.h85 static CCValAssign getReg(unsigned ValNo, MVT ValVT, MCRegister Reg,
92 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, MCRegister Reg, in getCustomReg()
116 void convertToReg(MCRegister Reg) { Data = Register(Reg); } in convertToReg()
257 bool isAllocated(MCRegister Reg) const { in isAllocated()
309 LLVM_ABI bool IsShadowAllocatedReg(MCRegister Reg) const;
332 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg()
334 return MCRegister(); in AllocateReg()
340 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg()
342 return MCRegister(); in AllocateReg()
351 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
[all …]
H A DRegAllocEvictionAdvisor.h108 virtual MCRegister tryFindEvictionCandidate(
115 canEvictHintInterference(const LiveInterval &VirtReg, MCRegister PhysReg,
120 bool isUnusedCalleeSavedReg(MCRegister PhysReg) const;
125 bool canReassign(const LiveInterval &VirtReg, MCRegister FromReg) const;
136 bool canAllocatePhysReg(unsigned CostPerUseLimit, MCRegister PhysReg) const;
286 MCRegister tryFindEvictionCandidate(const LiveInterval &,
289 bool canEvictHintInterference(const LiveInterval &, MCRegister,
291 bool canEvictInterferenceBasedOnCost(const LiveInterval &, MCRegister, bool,
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp58 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
59 ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
70 MCRegister parseRegisterName(MCRegister (*matchFn)(StringRef));
71 MCRegister parseRegisterName();
72 MCRegister parseRegister(bool RestoreOnFailure = false);
81 MCRegister toDREG(MCRegister Reg, unsigned From = AVR::sub_lo) { in toDREG()
115 AVROperand(MCRegister Reg, SMLoc const &S, SMLoc const &E) in AVROperand()
119 AVROperand(MCRegister Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E) in AVROperand()
123 MCRegister Reg;
197 MCRegister getReg() const override { in getReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h37 bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
38 bool isUserReservedReg(const MachineFunction &MF, MCRegister Reg) const;
39 bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const;
101 MCRegister PhysReg) const override;
103 MCRegister PhysReg) const override;
131 MCRegister Reg) const override;
145 bool regNeedsCFI(MCRegister Reg, MCRegister &RegToUseForCFI) const;
156 bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const override;
158 virtual bool isIgnoredCVReg(MCRegister LLVMReg) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp48 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
49 ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
104 MCRegister Reg;
109 MCRegister Reg;
119 MSP430Operand(KindTy Kind, MCRegister Reg, SMLoc const &S, SMLoc const &E) in MSP430Operand()
123 MSP430Operand(MCRegister Reg, MCExpr const *Expr, SMLoc const &S, in MSP430Operand()
186 MCRegister getReg() const override { in getReg()
191 void setReg(MCRegister RegNo) { in setReg()
200 static std::unique_ptr<MSP430Operand> CreateReg(MCRegister Reg, SMLoc S, in CreateReg()
211 CreateMem(MCRegister Reg, const MCExpr *Val, SMLoc S, SMLoc E) { in CreateMem()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h135 unsigned getDuplexRegisterNumbering(MCRegister Reg);
234 bool isDblRegForSubInst(MCRegister Reg);
263 bool isIntReg(MCRegister Reg);
266 bool isIntRegForSubInst(MCRegister Reg);
292 bool isPredReg(MCRegisterInfo const &MRI, MCRegister Reg);
337 PredicateInfo(MCRegister Register, unsigned Operand, bool PredicatedTrue) in PredicateInfo()
340 MCRegister Register;
363 unsigned SubregisterBit(MCRegister Consumer, MCRegister Producer,
364 MCRegister Producer2);
366 bool IsVecRegSingle(MCRegister VecReg);
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h50 MCRegister RegNo;
63 MCRegister SegReg;
65 MCRegister BaseReg;
66 MCRegister DefaultBaseReg;
67 MCRegister IndexReg;
169 MCRegister getReg() const override { in getReg()
188 MCRegister getMemSegReg() const { in getMemSegReg()
192 MCRegister getMemBaseReg() const { in getMemBaseReg()
196 MCRegister getMemDefaultBaseReg() const { in getMemDefaultBaseReg()
200 MCRegister getMemIndexReg() const { in getMemIndexReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVCallingConv.cpp246 if (MCRegister Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
267 if (MCRegister Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
281 static MCRegister allocateRVVReg(MVT ValVT, unsigned ValNo, CCState &State, in allocateRVVReg()
289 if (MCRegister Reg = State.AllocateReg(RISCV::V0)) in allocateRVVReg()
353 if (MCRegister Reg = State.AllocateReg(StaticChainReg)) { in CC_RISCV()
392 if (MCRegister Reg = State.AllocateReg(ArgFPR16s)) { in CC_RISCV()
399 if (MCRegister Reg = State.AllocateReg(ArgFPR32s)) { in CC_RISCV()
406 if (MCRegister Reg = State.AllocateReg(ArgFPR64s)) { in CC_RISCV()
413 if (MCRegister Reg = State.AllocateReg(getArgGPR16s(ABI))) { in CC_RISCV()
420 if (MCRegister Reg = State.AllocateReg(getArgGPR32s(ABI))) { in CC_RISCV()
[all …]

12345678910>>...15