| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 39 class MCInstrDesc; variable
374 const MCInstrDesc &MCID) { in BuildMI()
383 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
396 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
415 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
427 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
438 const MCInstrDesc &MCID, Register DestReg) { in BuildMI()
448 const MCInstrDesc &MCID) { in BuildMI()
460 const MCInstrDesc &MCID) { in BuildMI()
471 const MCInstrDesc &MCID) { in BuildMI()
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| H A D | DFAPacketizer.h | 45 class MCInstrDesc; variable
103 bool canReserveResources(const MCInstrDesc *MID);
107 void reserveResources(const MCInstrDesc *MID);
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.h | 25 class MCInstrDesc; variable
56 const MCInstrDesc &II,
70 const MCInstrDesc *II,
81 const MCInstrDesc *II,
114 const MCInstrDesc &DbgValDesc,
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| H A D | InstrEmitter.cpp | 129 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); in EmitCopyFromReg()
187 const MCInstrDesc &II, in CreateVirtualRegisters()
318 const MCInstrDesc *II, in AddRegisterOperand()
327 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
398 unsigned IIOpNum, const MCInstrDesc *II, in AddOperand()
639 const MCInstrDesc &II = TII->get(TargetOpcode::COPY); in EmitCopyToRegClassNode()
658 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
752 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, in AddDbgValueLocationOps()
789 const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF); in EmitDbgInstrRef()
921 const MCInstrDesc &Desc = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgNoLocation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCHazardRecognizers.cpp | 29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother()
175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType()
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| H A D | PPCExpandAtomicPseudoInsts.cpp | 52 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
53 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
119 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicRMW128()
120 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicRMW128()
217 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicCmpSwap128()
218 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicCmpSwap128()
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| H A D | PPCFrameLowering.cpp | 660 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 in emitPrologue()
662 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD in emitPrologue()
664 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU in emitPrologue()
666 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX in emitPrologue()
668 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitPrologue()
670 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 in emitPrologue()
672 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 in emitPrologue()
674 const MCInstrDesc &MoveFromCondRegInst = TII.get(isPPC64 ? PPC::MFCR8 in emitPrologue()
676 const MCInstrDesc &StoreWordInst = TII.get(isPPC64 ? PPC::STW8 : PPC::STW); in emitPrologue()
677 const MCInstrDesc &HashST = in emitPrologue()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrInfo.h | 34 const MCInstrDesc *LastDesc; // Raw array to allow static init'n
49 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
64 const MCInstrDesc &get(unsigned Opcode) const { in get()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 20 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, in mayAffectControlFlow()
32 bool MCInstrDesc::hasImplicitDefOfPhysReg(MCRegister Reg, in hasImplicitDefOfPhysReg()
40 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, MCRegister Reg, in hasDefOfPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 689 ComponentProps(const MCInstrDesc &OpDesc, bool VOP3Layout = false);
870 ComponentInfo(const MCInstrDesc &OpDesc,
877 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps,
896 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY) in InstInfo()
953 VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
965 unsigned getTemporalHintType(const MCInstrDesc TID);
1564 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1567 bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1570 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1573 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86EncodingOptimization.h | 17 class MCInstrDesc; variable
19 bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc);
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 55 bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) { in canReserveResources()
64 void DFAPacketizer::reserveResources(const MCInstrDesc *MID) { in reserveResources()
74 const MCInstrDesc &MID = MI.getDesc(); in canReserveResources()
81 const MCInstrDesc &MID = MI.getDesc(); in reserveResources()
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| H A D | ScoreboardHazardRecognizer.cpp | 122 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType()
177 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 171 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isPredicated()
177 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isCPSRDefined()
187 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, in evaluateBranchTarget()
418 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); in evaluateBranch()
445 evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode_i12()
463 evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode3()
483 evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5()
502 evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5FP16()
522 evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT2_i8s4()
543 evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT2_pc()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 159 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
160 SmallVectorImpl<const MCInstrDesc*> &ReplInstrMCID);
217 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst()
218 SmallVectorImpl<const MCInstrDesc*> &InstDescRepl) { in shouldReplaceInst()
274 const MCInstrDesc* OriginalMCID; in shouldExitEarly()
275 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in shouldExitEarly()
353 const MCInstrDesc *MulMCID, *DupMCID; in optimizeVectElement()
419 SmallVector<const MCInstrDesc*, 2> ReplInstrMCID; in optimizeVectElement()
512 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in optimizeLdStInterleave()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.h | 198 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) { in getVLOpNum()
216 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) { in getSEWOpNum()
225 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) { in getVecPolicyOpNum()
232 static inline int getFRMOpNum(const MCInstrDesc &Desc) { in getFRMOpNum()
247 static inline int getVXRMOpNum(const MCInstrDesc &Desc) { in getVXRMOpNum()
263 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) { in isFirstDefTiedToFirstUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoadStoreWidening.cpp | 613 const MCInstrDesc &CombD = TII->get(Hexagon::A2_combinew); in createWideStores()
620 const MCInstrDesc &StD = TII->get(Hexagon::S2_storerd_pi); in createWideStores()
626 const MCInstrDesc &StD = TII->get(Hexagon::S2_storerd_io); in createWideStores()
648 const MCInstrDesc &TfrD = TII->get(Hexagon::A2_tfrsi); in createWideStores()
653 const MCInstrDesc &CombD = TII->get(Hexagon::A4_combineir); in createWideStores()
660 const MCInstrDesc &CombD = TII->get(Hexagon::A4_combineii); in createWideStores()
664 const MCInstrDesc &StD = TII->get(Hexagon::S2_storerd_io); in createWideStores()
675 const MCInstrDesc &StD = TII->get(WOpc); in createWideStores()
679 const MCInstrDesc &TfrD = TII->get(Hexagon::A2_tfrsi); in createWideStores()
690 const MCInstrDesc &StD = TII->get(WOpc); in createWideStores()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ReturnThunks.cpp | 82 const MCInstrDesc &CS = ST.getInstrInfo()->get(X86::CS_PREFIX); in runOnMachineFunction()
83 const MCInstrDesc &JMP = ST.getInstrInfo()->get(X86::TAILJMPd); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 423 const MCInstrDesc &DefMCID,
427 const MCInstrDesc &DefMCID,
431 const MCInstrDesc &UseMCID,
435 const MCInstrDesc &UseMCID,
439 const MCInstrDesc &DefMCID,
441 const MCInstrDesc &UseMCID,
447 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
449 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;
897 const MCInstrDesc &Desc = TII->get(Opcode); in isLegalAddressImm()
985 const MCInstrDesc &MCID = MI->getDesc(); in isMVEVectorInstruction()
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| H A D | MLxExpansionPass.cpp | 184 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
284 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
339 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
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| H A D | ARMHazardRecognizer.cpp | 29 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
50 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
53 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrBuilder.h | 63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
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| H A D | M68kInstrInfo.h | 317 const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const;
320 bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
327 bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16InstrInfo.h | 24 class MCInstrDesc; variable
99 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/ |
| H A D | SPIRVInstPrinter.cpp | 119 const MCInstrDesc &MCDesc = MII.get(OpCode); in printInst()
285 const MCInstrDesc &MCDesc = MII.get(MI->getOpcode()); in printOpExtInst()
300 const MCInstrDesc &MCDesc = MII.get(MI->getOpcode()); in printOpDecorate()
362 const MCInstrDesc &MCDesc = MII.get(MI->getOpcode()); in printUnknownType()
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