| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 33 LiveIntervals *LIS; member in __anon314e3b690111::SIOptimizeExecMaskingPreRA
91 LiveIntervals *LIS, Register Reg, in isDefBetween() argument
93 SlotIndex AndIdx = LIS->getInstructionIndex(And).getRegSlot(); in isDefBetween()
94 SlotIndex SelIdx = LIS->getInstructionIndex(Sel).getRegSlot(); in isDefBetween()
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(Unit), AndIdx, SelIdx)) in isDefBetween()
132 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS); in optimizeVcndVcmpPair()
148 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS); in optimizeVcndVcmpPair()
165 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS); in optimizeVcndVcmpPair()
184 if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And)) in optimizeVcndVcmpPair()
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| H A D | SILowerControlFlow.cpp | 75 LiveIntervals *LIS = nullptr; member in __anon0c226a110111::SILowerControlFlow
277 if (!LIS) { in emitIf()
282 LIS->InsertMachineInstrInMaps(*CopyExec); in emitIf()
286 LIS->ReplaceMachineInstrInMaps(MI, *And); in emitIf()
289 LIS->InsertMachineInstrInMaps(*Xor); in emitIf()
290 LIS->InsertMachineInstrInMaps(*SetExec); in emitIf()
291 LIS->InsertMachineInstrInMaps(*NewBr); in emitIf()
293 LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC); in emitIf()
300 LIS->createAndComputeVirtRegInterval(Tmp); in emitIf()
302 LIS->createAndComputeVirtRegInterval(CopyReg); in emitIf()
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| H A D | SILowerSGPRSpills.cpp | 39 LiveIntervals *LIS = nullptr; member in __anoneec5f4eb0111::SILowerSGPRSpills
55 void extendWWMVirtRegLiveness(MachineFunction &MF, LiveIntervals *LIS);
88 LiveIntervals *LIS) { in insertCSRSaves() argument
122 if (LIS) in insertCSRSaves()
123 LIS->removeAllRegUnitsForPhysReg(Reg); in insertCSRSaves()
131 SlotIndexes *Indexes, LiveIntervals *LIS) { in insertCSRRestores() argument
161 if (LIS) in insertCSRRestores()
162 LIS->removeAllRegUnitsForPhysReg(Reg); in insertCSRRestores()
247 insertCSRSaves(*SaveBlock, CSI, Indexes, LIS); in spillCalleeSavedRegs()
254 insertCSRRestores(*RestoreBlock, CSI, Indexes, LIS); in spillCalleeSavedRegs()
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| H A D | GCNPreRAOptimizations.cpp | 45 LiveIntervals *LIS; member in __anon021209ff0111::GCNPreRAOptimizations
179 LIS->removeInterval(RegToUpdate); in processReg()
180 LIS->createAndComputeVirtRegInterval(RegToUpdate); in processReg()
194 if (SlotIndex::isEarlierInstr(LIS->getInstructionIndex(*Def1), in processReg()
195 LIS->getInstructionIndex(*Def0))) in processReg()
198 LIS->RemoveMachineInstrFromMaps(*Def0); in processReg()
199 LIS->RemoveMachineInstrFromMaps(*Def1); in processReg()
206 LIS->InsertMachineInstrInMaps(*NewI); in processReg()
207 LIS->removeInterval(Reg); in processReg()
208 LIS->createAndComputeVirtRegInterval(Reg); in processReg()
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| H A D | SIWholeQuadMode.cpp | 156 LiveIntervals *LIS; member in __anonf56fbe7e0111::SIWholeQuadMode
320 LiveQueryResult UseLRQ = LR.Query(LIS->getInstructionIndex(UseMI)); in markDefs()
359 const MachineBasicBlock *MBB = LIS->getMBBFromIndex(Value->def); in markDefs()
367 if (const VNInfo *VN = LR.getVNInfoBefore(LIS->getMBBEndIdx(*PI))) { in markDefs()
377 MachineInstr *MI = LIS->getInstructionFromIndex(Value->def); in markDefs()
403 LiveQueryResult LRQ = LR.Query(LIS->getInstructionIndex(*MI)); in markDefs()
450 LiveRange &LR = LIS->getInterval(Reg); in markOperand()
457 LiveRange &LR = LIS->getRegUnit(Unit); in markOperand()
458 const VNInfo *Value = LR.Query(LIS->getInstructionIndex(MI)).valueIn(); in markOperand()
737 LIS->InsertMachineInstrInMaps(*Save); in saveSCC()
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| H A D | GCNRegPressure.h | 151 const LiveIntervals &LIS;
157 GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {} in GCNRPTracker()
176 GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
188 reset(MRI, llvm::getLiveRegs(SI, LIS, MRI)); in reset()
194 LIS.getSlotIndexes()->getMBBEndIdx(&MBB)); in reset()
199 reset(MI.getMF()->getRegInfo(), LIS.getInstructionIndex(MI).getDeadSlot()); in reset()
264 const LiveIntervals &LIS,
270 GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
280 getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) { in getLiveRegMap() argument
283 auto &SII = *LIS.getSlotIndexes(); in getLiveRegMap()
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| H A D | GCNIterativeScheduler.cpp | 47 const LiveIntervals *LIS, in printRegion() argument
56 if (!I->isDebugInstr() && LIS) in printRegion()
57 OS << LIS->getInstructionIndex(*I); in printRegion()
63 if (!I->isDebugInstr() && LIS) in printRegion()
64 OS << LIS->getInstructionIndex(*I); in printRegion()
69 if (LIS) OS << LIS->getInstructionIndex(*End) << '\t'; in printRegion()
78 const LiveIntervals *LIS) { in printLivenessInfo() argument
82 const auto LiveIns = getLiveRegsBefore(*Begin, *LIS); in printLivenessInfo()
86 const auto LiveOuts = getLiveRegsAfter(*BottomMI, *LIS); in printLivenessInfo()
95 printRegion(OS, R->Begin, R->End, LIS, 1); in printRegions()
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| H A D | GCNRegPressure.cpp | 259 const MachineInstr &MI, const LiveIntervals &LIS, in collectVirtualRegUses() argument
275 auto &LI = LIS.getInterval(Reg); in collectVirtualRegUses()
283 InstrSI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex(); in collectVirtualRegUses()
295 const LiveIntervals &LIS, in getLiveLaneMask() argument
297 return getLiveLaneMask(LIS.getInterval(Reg), SI, MRI); in getLiveLaneMask()
316 const LiveIntervals &LIS, in getLiveRegs() argument
321 if (!LIS.hasInterval(Reg)) in getLiveRegs()
323 auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI); in getLiveRegs()
339 LiveRegs = After ? getLiveRegsAfter(MI, LIS) in reset()
340 : getLiveRegsBefore(MI, LIS); in reset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 102 LiveIntervals &LIS) { in convertImplicitDefToConstZero() argument
267 const LiveIntervals &LIS) { in getVRegDef() argument
273 if (const VNInfo *ValNo = LIS.getInterval(Reg).getVNInfoBefore( in getVRegDef()
274 LIS.getInstructionIndex(*Insert))) in getVRegDef()
275 return LIS.getInstructionFromIndex(ValNo->def); in getVRegDef()
285 LiveIntervals &LIS) { in hasOneNonDBGUse() argument
291 const LiveInterval &LI = LIS.getInterval(Reg); in hasOneNonDBGUse()
293 LI.getVNInfoAt(LIS.getInstructionIndex(*Def).getRegSlot()); in hasOneNonDBGUse()
296 const auto &Result = LI.Query(LIS.getInstructionIndex(*I.getParent())); in hasOneNonDBGUse()
439 LiveIntervals &LIS, in oneUseDominatesOtherUses() argument
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| H A D | WebAssemblyMemIntrinsicResults.cpp | 88 LiveIntervals &LIS) { in replaceDominatedUses() argument
91 LiveInterval *FromLI = &LIS.getInterval(FromReg); in replaceDominatedUses()
92 LiveInterval *ToLI = &LIS.getInterval(ToReg); in replaceDominatedUses()
94 SlotIndex FromIdx = LIS.getInstructionIndex(MI).getRegSlot(); in replaceDominatedUses()
108 SlotIndex WhereIdx = LIS.getInstructionIndex(*Where); in replaceDominatedUses()
133 LIS.extendToIndices(*ToLI, Indices); in replaceDominatedUses()
136 LIS.shrinkToUses(FromLI); in replaceDominatedUses()
150 MachineDominatorTree &MDT, LiveIntervals &LIS, in optimizeCall() argument
173 return replaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT, LIS); in optimizeCall()
188 auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS(); in runOnMachineFunction() local
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| H A D | WebAssemblyOptimizeLiveIntervals.cpp | 80 auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS(); in runOnMachineFunction() local
96 LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs); in runOnMachineFunction()
116 LiveInterval &LI = LIS.getInterval(MI.getOperand(0).getReg()); in runOnMachineFunction()
117 LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(MI).getRegSlot()); in runOnMachineFunction()
118 LIS.RemoveMachineInstrFromMaps(MI); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRangeEdit.cpp | 40 LiveInterval &LI = LIS.createEmptyInterval(VReg); in createEmptyIntervalFrom()
47 LiveInterval &OldLI = LIS.getInterval(OldReg); in createEmptyIntervalFrom()
48 VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator(); in createEmptyIntervalFrom()
67 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
86 LiveInterval &OrigLI = LIS.getInterval(Original); in scanRemattable()
90 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); in scanRemattable()
123 LiveInterval &li = LIS.getInterval(MO.getReg()); in allUsesAvailableAt()
169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
198 return LIS.ReplaceMachineInstrInMaps(*ReplaceIndexMI, *MI).getRegSlot(); in rematerializeAt()
199 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot(); in rematerializeAt()
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| H A D | SplitKit.cpp | 64 : LIS(lis), LastInsertPoint(BBNum) {} in InsertPointAnalysis()
71 SlotIndex MBBEnd = LIS.getMBBEndIdx(&MBB); in computeLastInsertPoint()
90 LIP.first = LIS.getInstructionIndex(*FirstTerm); in computeLastInsertPoint()
103 LIP.second = LIS.getInstructionIndex(MI); in computeLastInsertPoint()
115 return LIS.isLiveInToMBB(CurLI, EHPad); in computeLastInsertPoint()
127 if (auto *I = LIS.getInstructionFromIndex(LIP.second)) in computeLastInsertPoint()
146 if (LIP == LIS.getMBBEndIdx(&MBB)) in getLastInsertPointIter()
148 return LIS.getInstructionFromIndex(LIP); in getLastInsertPointIter()
157 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli), in SplitAnalysis()
181 UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot()); in analyzeUses()
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| H A D | PHIElimination.cpp | 71 LiveIntervals *LIS = nullptr; member in __anonf60509ee0111::PHIEliminationImpl
125 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr; in PHIEliminationImpl()
132 LIS(AM.getCachedResult<LiveIntervalsAnalysis>(MF)), in PHIEliminationImpl()
209 if (!DisableEdgeSplitting && (LV || LIS)) { in run()
247 if (LV || LIS) in run()
258 if (LIS) in run()
259 LIS->RemoveMachineInstrFromMaps(*DefMI); in run()
266 if (LIS) in run()
267 LIS->RemoveMachineInstrFromMaps(*I.first); in run()
461 if (LIS) { in LowerPHINode()
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| H A D | InlineSpiller.cpp | 82 LiveIntervals &LIS; member in __anon2f89086e0111::HoistSpillHelper
134 : MF(mf), LIS(pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()), in HoistSpillHelper()
141 IPA(LIS, mf.getNumBlockIDs()) {} in HoistSpillHelper()
152 LiveIntervals &LIS; member in __anon2f89086e0111::InlineSpiller
192 : MF(MF), LIS(Pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()), in InlineSpiller()
310 static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) { in getVDefInterval() argument
313 LIS.getInterval(MO.getReg()); in getVDefInterval()
333 if (!LIS.intervalIsInOneMBB(SnipLI)) in isSnippet()
340 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); in isSnippet()
398 LiveInterval &SnipLI = LIS.getInterval(SnipReg); in collectRegsToSpill()
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| H A D | RegAllocPBQP.cpp | 162 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
169 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
181 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
184 void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
193 LiveIntervals &LIS = G.getMetadata().LIS; in apply() local
201 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight(); in apply()
310 LiveIntervals &LIS = G.getMetadata().LIS; in apply() local
334 LiveInterval &LI = LIS.getInterval(VReg); in apply()
529 PBQPVirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM, in PBQPVirtRegAuxInfo() argument
532 : VirtRegAuxInfo(MF, LIS, VRM, Loops, MBFI) {} in PBQPVirtRegAuxInfo()
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| H A D | RegisterCoalescer.cpp | 131 LiveIntervals *LIS = nullptr; member in __anonf9586a8a0111::RegisterCoalescer
347 if (LIS->shrinkToUses(LI, Dead)) { in shrinkToUses()
351 LIS->splitSeparateComponents(*LI, SplitLIs); in shrinkToUses()
361 LIS->RemoveMachineInstrFromMaps(*MI); in deleteInstr()
606 LiveRangeEdit(nullptr, NewRegs, *MF, *LIS, in eliminateDeadDefs()
621 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); in adjustCopiesBackFrom()
623 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); in adjustCopiesBackFrom()
624 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot(); in adjustCopiesBackFrom()
660 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def); in adjustCopiesBackFrom()
674 LIS->getInstructionFromIndex(ValS->end.getPrevSlot()); in adjustCopiesBackFrom()
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| H A D | RenameIndependentSubregs.cpp | 72 SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR, in SubRangeInfo()
74 : ConEQ(LIS), SR(&SR), Index(Index) {} in SubRangeInfo()
104 LiveIntervals *LIS = nullptr; member in __anon60dd69b50111::RenameIndependentSubregs
143 LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg); in INITIALIZE_PASS_DEPENDENCY()
162 SubRangeInfos.push_back(SubRangeInfo(*LIS, SR, NumComponents)); in findComponents()
189 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent()); in findComponents()
223 SlotIndex Pos = LIS->getInstructionIndex(*MI); in rewriteOperands()
271 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); in distribute()
303 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); in computeMainRangesFixFlags()
304 const SlotIndexes &Indexes = *LIS->getSlotIndexes(); in computeMainRangesFixFlags()
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| H A D | LiveDebugVariables.cpp | 310 ArrayRef<unsigned> SpillOffsets, LiveIntervals &LIS,
318 LiveIntervals &LIS);
449 LiveIntervals &LIS);
465 MachineRegisterInfo &MRI, LiveIntervals &LIS);
470 LiveIntervals &LIS, LexicalScopes &LS);
475 LiveIntervals &LIS);
486 void emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
507 LiveIntervals &LIS, const TargetInstrInfo &TII,
522 void emitDebugLabel(LiveIntervals &LIS, const TargetInstrInfo &TII,
536 LiveIntervals *LIS; member in __anon093131440411::LDVImpl
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| H A D | TwoAddressInstructionPass.cpp | 99 LiveIntervals *LIS = nullptr; member in __anon97cd436d0111::TwoAddressInstructionImpl
273 LIS(MFAM.getCachedResult<LiveIntervalsAnalysis>(Func)), in INITIALIZE_PASS_DEPENDENCY()
289 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr; in TwoAddressInstructionImpl()
388 SlotIndex useIdx = LIS->getInstructionIndex(*MI); in isPlainlyKilled()
404 if (LIS && !LIS->isNotInMIMap(*MI)) { in isPlainlyKilled()
406 return isPlainlyKilled(MI, LIS->getInterval(Reg)); in isPlainlyKilled()
411 return isPlainlyKilled(MI, LIS->getRegUnit(U)); in isPlainlyKilled()
790 MachineInstr *NewMI = TII->convertToThreeAddress(*mi, LV, LIS); in convertInstTo3Addr()
912 if (!LV && !LIS) in rescheduleMIBelowKill()
922 if (LIS) { in rescheduleMIBelowKill()
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| H A D | CalcSpillWeights.cpp | 43 calculateSpillWeightAndHint(LIS.getInterval(Reg)); in calculateSpillWeightsAndHints()
83 const LiveIntervals &LIS, in isRematerializable() argument
96 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); in isRematerializable()
116 const LiveInterval &SrcLI = LIS.getInterval(Reg); in isRematerializable()
122 MI = LIS.getInstructionFromIndex(VNI->def); in isRematerializable()
176 const LiveInterval &OrigInt = LIS.getInterval(Original); in weightCalcHelper()
193 MachineBasicBlock *LocalMBB = LIS.getMBBFromIndex(*End); in weightCalcHelper()
194 assert(LocalMBB == LIS.getMBBFromIndex(*Start) && in weightCalcHelper()
234 SlotIndex SI = LIS.getInstructionIndex(*MI); in weightCalcHelper()
278 if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB)) in weightCalcHelper()
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| H A D | RegAllocBase.cpp | 63 LIS = &lis; in init()
79 enqueue(&LIS->getInterval(Reg)); in seedLiveRegs()
96 LIS->removeInterval(VirtReg->reg()); in allocatePhysRegs()
145 assert(LIS->hasInterval(Reg)); in allocatePhysRegs()
147 LiveInterval *SplitVirtReg = &LIS->getInterval(Reg); in allocatePhysRegs()
153 LIS->removeInterval(SplitVirtReg->reg()); in allocatePhysRegs()
168 LIS->RemoveMachineInstrFromMaps(*DeadInst); in postOptimization()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInsertVSETVLI.cpp | 50 const LiveIntervals *LIS) { in getVNInfoFromReg() argument
52 if (!LIS) in getVNInfoFromReg()
54 auto &LI = LIS->getInterval(Reg); in getVNInfoFromReg()
55 SlotIndex SI = LIS->getSlotIndexes()->getInstructionIndex(MI); in getVNInfoFromReg()
587 const MachineInstr *getAVLDefMI(const LiveIntervals *LIS) const { in getAVLDefMI()
589 if (!LIS || getAVLVNInfo()->isPHIDef()) in getAVLDefMI()
591 auto *MI = LIS->getInstructionFromIndex(getAVLVNInfo()->def); in getAVLDefMI()
615 bool hasNonZeroAVL(const LiveIntervals *LIS) const { in hasNonZeroAVL()
619 if (auto *DefMI = getAVLDefMI(LIS)) in hasNonZeroAVL()
628 const LiveIntervals *LIS) const { in hasEquallyZeroAVL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 67 LiveIntervals *LIS; member
109 SlotIndex FMAIdx = LIS->getInstructionIndex(MI); in processBlock()
112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
118 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def); in processBlock()
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
213 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) in processBlock()
281 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg); in processBlock()
299 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg); in processBlock()
306 NewFMAInt.getNextValue(AI.start, LIS->getVNInfoAllocator()); in processBlock()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | CalcSpillWeights.h | 47 LiveIntervals &LIS; variable
57 VirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS, in VirtRegAuxInfo() argument
60 : MF(MF), LIS(LIS), VRM(VRM), Loops(Loops), MBFI(MBFI) {} in VirtRegAuxInfo()
79 const LiveIntervals &LIS,
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