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Searched refs:HW (Results 1 – 25 of 163) sorted by relevance

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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/
H A Dfp_div_impl.inc27 #define HW (typeWidth / 2)
29 #define loMask (REP_C(-1) >> HW)
120 // Let b_hw be an infinitely precise number obtained from the highest (HW-1)
122 // half_rep_t-sized b_UQ1_hw represented in UQ1.(HW-1) that is a **truncated**
129 // <= abs(e_n) + 2 * 2^-HW
139 const half_rep_t b_UQ1_hw = bSignificand >> (significandBits + 1 - HW);
141 // C is (3/4 + 1/sqrt(2)) - 1 truncated to W0 fractional bits as UQ0.HW
142 // with W0 being either 16 or 32 and W0 <= HW.
152 // HW is at least 32. Shifting into the highest bits if needed.
153 const half_rep_t C_hw = HALF_REP_C(0x7504F333) << (HW - 32);
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/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dmediatek,iommu.txt4 this M4U have two generations of HW architecture. Generation one uses flat
42 As above, The Multimedia HW will go through SMI and M4U while it
43 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
45 HW should go though the m4u for translation or bypass it and talk
48 Normally we specify a local arbiter(larb) for each multimedia HW
51 video decode local arbiter, all these ports are according to the video HW.
59 "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
60 "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
61 "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.
63 generation one m4u HW.
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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dinterface.txt17 "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
19 "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
20 "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
21 "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
22 "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
/freebsd/sys/dev/mlx5/mlx5_en/
H A Dmlx5_en_port_buffer.c66 mlx5e_dbg(HW, priv, "buffer %d: size=%d, xon=%d, xoff=%d, epsb=%d, lossy=%d\n", i, in mlx5e_port_query_buffer()
79 mlx5e_dbg(HW, priv, "total buffer size=%d, spare buffer size=%d\n", in mlx5e_port_query_buffer()
139 mlx5e_dbg(HW, priv, "%s: xoff=%d\n", __func__, xoff); in calculate_xoff()
255 mlx5e_dbg(HW, priv, "%s: change=%x\n", __func__, change); in mlx5e_port_manual_buffer_config()
294 mlx5e_dbg(HW, priv, "%s: buffer[%d]=%d\n", __func__, i, buffer_size[i]); in mlx5e_port_manual_buffer_config()
296 mlx5e_dbg(HW, priv, "%s: lossless buffer[%d] size cannot be zero\n", in mlx5e_port_manual_buffer_config()
305 mlx5e_dbg(HW, priv, "%s: total buffer requested=%d\n", __func__, total_used); in mlx5e_port_manual_buffer_config()
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmediatek,smi-common.txt5 Mediatek SMI have two generations of HW architecture, here is the list
29 - clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
30 for generation 2 smi HW as follows:
36 clock domain, this clock is only needed by generation 1 smi HW.
37 and these 2 option clocks for generation 2 smi HW:
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dqcom_hidma_mgmt.txt7 Each HIDMA HW instance consists of multiple DMA channels. These channels
37 Once a reset is applied to the HW, HW starts a timer for reset operation
38 to confirm. If reset is not completed within this time, HW reports reset
50 - compatible: must contain "qcom,hidma-1.0" for initial HW or
51 "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.
/freebsd/usr.bin/tip/tip/
H A Dcu.c105 HW = 1, DU = -1; in cumain()
174 if (HW && ttysetup(BR)) { in cumain()
187 if (!HW && ttysetup(BR)) { in cumain()
H A Dremote.c84 HW = 1; in getremcap()
143 if (!HW) in getremcap()
144 HW = (CU == NOSTR) || (DU && equal(DV, CU)); in getremcap()
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dreset.txt21 in hardware for a reset signal to affect multiple logically separate HW blocks
23 the DT node of each affected HW block, since if activated, an unrelated block
26 children of the bus are affected by the reset signal, or an individual HW
28 appropriate software access to the reset signals in order to manage the HW,
29 rather than to slavishly enumerate the reset signal that affects each HW
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-jaguar-pre-ict-tester.dtso79 * but GPIO3_C6 would catch this HW soldering issue.
92 * the loop doesn't exist on HW (soldering issue on
101 * but GPIO3_C6 would catch this HW soldering issue.
135 * the loop doesn't exist on HW (soldering issue on
145 * the loop doesn't exist on HW (soldering issue on
155 * the loop doesn't exist on HW (soldering issue on
165 * the loop doesn't exist on HW (soldering issue on
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dnvidia,tegra186-gpio.txt11 package balls is under the control of a separate pin controller HW block. Two
30 Tegra HW documentation describes a unified naming convention for all GPIOs
44 matches the HW documentation. The values chosen for the names are alphabetically
46 IDs and HW register offsets using a lookup table.
51 of the number of ports it implements. Note that the HW documentation refers to
52 both the overall controller HW module and the sets-of-ports as "controllers".
91 The interrupt outputs from the HW block, one per set of ports, in the
92 order the HW manual describes them. The number of entries required varies
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt40 SW need to set priorities for various throttle, the HW arbiter can select
100 than it, it will trigger the HW throttle event.
124 * the HW will skip cpu clock's pulse in 85% depth,
137 * the HW will skip cpu clock's pulse in 50% depth,
149 * If these two devices are triggered in same time, the HW throttle
178 * the HW will skip cpu clock's pulse in HIGH level
189 * the HW will skip cpu clock's pulse in MED level
199 * If these two devices are triggered in same time, the HW throttle
/freebsd/sys/contrib/device-tree/Bindings/arc/
H A Dpct.txt8 * The ARC 700 PCT does not support interrupts; although HW events may be
9 counted, the HW events themselves cannot serve as a trigger for a sample.
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsnps,dwc-qos-ethernet.txt9 entries in properties are marked as optional, or only required in specific HW
28 The EQOS transmit path clock. The HW signal name is clk_tx_i.
33 The EQOS receive path clock. The HW signal name is clk_rx_i.
44 APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
48 separate clock for the master and slave bus interfaces. The HW signal name
51 The PTP reference clock. The HW signal name is clk_ptp_ref_i.
92 - "eqos". The reset to the entire module. The HW signal name is hreset_n
H A Dbrcm,systemport.txt21 - systemport,num-txq: number of HW transmit queues, an integer
22 - systemport,num-rxq: number of HW receive queues, an integer
H A Dcavium-pip.txt41 Value range is 1-31, and mapping to the actual delay varies depending on HW.
44 Value range is 1-31, and mapping to the actual delay varies depending on HW.
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dmediatek-vpu.txt3 Video Processor Unit is a HW video controller. It controls HW Codec including
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/PDB/Native/
H A DTpiStreamBuilder.cpp198 BinaryStreamWriter HW(*HVS); in commit() local
200 if (auto EC = HW.writeStreamRef(*HashValueStream)) in commit()
205 if (auto EC = HW.writeObject(IndexOffset)) in commit()
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr9a07g044c2-smarc.dts24 /* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
32 #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dnvidia,tegra20-ictlr.txt7 The HW block exposes a number of interrupt controllers, each
25 - Because this HW ultimately routes interrupts to the GIC, the
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Datmel-crypto.txt1 * Atmel HW cryptographic accelerators
3 These are the HW cryptographic accelerators found on some Atmel products.
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dgeneric.txt8 controllers should default to their maximum HW
19 default to HW capability.
/freebsd/contrib/llvm-project/compiler-rt/lib/orc/tests/unit/
H A Dsimple_packed_serialization_test.cpp111 const char *HW = "Hello, world!"; in TEST() local
112 blobSerializationRoundTrip<SPSString, std::string_view>(std::string_view(HW)); in TEST()
/freebsd/sys/contrib/device-tree/Bindings/rng/
H A Dst,rng.txt1 STMicroelectronics HW Random Number Generator
/freebsd/sys/contrib/device-tree/Bindings/arm/omap/
H A Diva.txt3 The IVA contain various audio, video or imaging HW accelerator

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