Home
last modified time | relevance | path

Searched refs:GPR (Results 1 – 25 of 213) sorted by relevance

123456789

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoSFB.td17 def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst),
18 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
19 GPR:$falsev, GPR:$truev),
20 [(set GPR:$dst,
21 (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),
22 GPR:$rhs, cond,
23 (XLenVT GPR:$truev),
24 GPR:$falsev))]>,
37 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
40 (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),
[all …]
H A DRISCVGISel.td44 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)),
45 (SLTIU GPR:$rs1, simm12:$imm12)>;
46 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
47 (SLTU GPR:$rs1, GPR:$rs2)>;
48 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12:$imm12)),
49 (SLTI GPR:$rs1, simm12:$imm12)>;
50 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
51 (SLT GPR:$rs1, GPR:$rs2)>;
56 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty 0))), (SLTIU GPR:$rs1, 1)>;
57 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty simm12Plus1:$imm12))),
[all …]
H A DRISCVInstrInfoA.td21 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
36 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
49 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
173 def : StPat<relaxed_store<atomic_store_8>, SB, GPR, XLenVT>;
174 def : StPat<relaxed_store<atomic_store_16>, SH, GPR, XLenVT>;
175 def : StPat<relaxed_store<atomic_store_32>, SW, GPR, XLenVT>;
186 def : StPat<relaxed_store<atomic_store_64>, SD, GPR, i64>;
242 class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
243 (ins GPR:$addr, GPR:$incr, ixlenimm:$ordering), []> {
251 : Pseudo<(outs GPR:$res, GPR:$scratch),
[all …]
H A DRISCVInstrInfoXTHead.td96 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
105 : RVInstRBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
106 (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
115 : RVInstIShift<funct5, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
116 (ins GPR:$rs1, uimmlog2xlen:$shamt),
121 : RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
122 (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
133 (outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">;
137 : RVInstIShiftW<funct7, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
138 (ins GPR:$rs1, uimm5:$shamt),
[all …]
H A DRISCVInstrInfoXVentana.td20 : RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
21 (ins GPR:$rs1, GPR:$rs2), opcodestr,
32 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
33 (VT_MASKC GPR:$rs1, GPR:$rc)>;
34 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
35 (VT_MASKCN GPR:$rs1, GPR:$rc)>;
37 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
38 (VT_MASKC GPR:$rs1, GPR:$rc)>;
39 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
40 (VT_MASKCN GPR:$rs1, GPR:$rc)>;
[all …]
H A DRISCVInstrInfoZb.td254 : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
262 : RVInstIShift<imm11_7, funct3, opcode, (outs GPR:$rd),
263 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
459 def : InstAlias<"zext.w $rd, $rs", (ADD_UW GPR:$rd, GPR:$rs, X0)>;
464 (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
469 (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
474 (BSETI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
476 (BCLRI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
478 (BINVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
480 (BEXTI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
[all …]
H A DRISCVInstrInfoZa.td59 defm AMOCAS_W : AMO_cas_aq_rl<0b00101, 0b010, "amocas.w", GPR>;
67 defm AMOCAS_D_RV64 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPR>;
74 def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr),
75 (vt GPR:$cmp),
76 (vt GPR:$new)),
77 (!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
78 def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (vt GPR:$addr),
79 (vt GPR:$cmp),
80 (vt GPR:$new)),
81 (!cast<RVInst>(BaseInst#"_AQ") GPR:$cmp, GPR:$addr, GPR:$new)>;
[all …]
H A DRISCVInstrInfoZicond.td39 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
40 (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
41 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
42 (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
44 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
45 (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
46 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
47 (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
48 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
49 (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
[all …]
H A DRISCVInstrInfoXMips.td132 def MIPS_PREFETCH : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
139 def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
141 (MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 9)>;
143 def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
145 (MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 8)>;
150 def MIPS_CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
151 (ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
157 def : Pat<(select (riscv_setne (XLenVT GPR:$rs2)),
158 (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
159 (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
[all …]
H A DRISCVInstrInfoXCV.td26 let MIOperandInfo = (ops GPR:$base, GPR:$offset);
67 : CVInstBitManipRII<funct2, funct3, (outs GPR:$rd),
68 (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
72 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
73 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
76 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
77 (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
84 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
107 : CVInstMacMulN<funct2, funct3, (outs GPR:$rd_wb),
108 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr> {
[all …]
H A DRISCVInstrInfo.td211 def GPRMemZeroOffset : MemOperand<GPR> {
216 def GPRMem : MemOperand<GPR>;
620 (ins GPR:$rs1, GPR:$rs2, bare_simm13_lsb0:$imm12),
631 class Load_ri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
636 : RVInstR<funct7, 0b100, OPC_SYSTEM, (outs GPR:$rd),
646 class Store_rri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
653 (ins GPR:$rs2, GPRMemZeroOffset:$rs1),
661 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
667 : RVInstIShift<imm11_7, funct3, OPC_OP_IMM, (outs GPR:$rd),
668 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
[all …]
H A DRISCVInstrInfoZimop.td47 : RVInstIMopr<imm7, imm5, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
53 : RVInstRMoprr<imm4, imm3, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
71 def : Pat<(XLenVT (riscv_mopr GPR:$rs1, (XLenVT i))),
72 (!cast<Instruction>("MOPR"#i) GPR:$rs1)>;
76 def : Pat<(XLenVT (riscv_moprr GPR:$rs1, GPR:$rs2, (XLenVT i))),
77 (!cast<Instruction>("MOPRR"#i) GPR:$rs1, GPR:$rs2)>;
H A DRISCVInstrInfoM.td100 def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
101 (assertzexti32 GPR:$rs2)), 0xffffffff),
102 (DIVU GPR:$rs1, GPR:$rs2)>;
103 def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
104 (assertzexti32 GPR:$rs2)), 0xffffffff),
105 (REMU GPR:$rs1, GPR:$rs2)>;
110 def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
111 (REMW GPR:$rs1, GPR:$rs2)>;
119 def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
120 (MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
H A DRISCVInstrInfoXAndes.td93 (ins GPR:$rs1, uimmlog2xlen:$cimm, bare_simm11_lsb0:$imm10),
117 : RVInst<(outs), (ins GPR:$rs1, uimm7:$cimm, bare_simm11_lsb0:$imm10),
141 : RVInst<(outs GPR:$rd),
142 (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
163 (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
173 (outs GPR:$rd), (ins GPR:$rs2, GPR:$rs1),
183 : RVInst<(outs GPR:$rd), (ins simm18:$imm18),
204 : RVInst<(outs GPR:$rd), (ins simm18_lsb0:$imm17),
224 : RVInst<(outs GPR:$rd), (ins simm19_lsb00:$imm17),
245 : RVInst<(outs GPR:$rd), (ins simm20_lsb000:$imm17),
[all …]
H A DRISCVInstrInfoD.td50 def FPR64INX : RegisterOperand<GPR> {
131 defm FCLASS_D : FPUnaryOp_r_m<0b1110001, 0b00000, 0b001, Ext, GPR, Ext.PrimaryTy,
136 defm FCVT_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b00000, Ext, GPR, Ext.PrimaryTy,
141 defm FCVT_WU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00001, Ext, GPR, Ext.PrimaryTy,
147 Ext.PrimaryTy, GPR, "fcvt.d.w">,
152 Ext.PrimaryTy, GPR, "fcvt.d.wu">,
157 defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, Ext, GPR, Ext.PrimaryTy,
161 defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, Ext, GPR, Ext.PrimaryTy,
165 defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, Ext, Ext.PrimaryTy, GPR,
169 defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, Ext, Ext.PrimaryTy, GPR,
[all …]
H A DRISCVInstrInfoZfbfmin.td32 def : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), GPR:$rhs, cond,
34 (Select_FPR16_Using_CC_GPR GPR:$lhs, GPR:$rhs,
39 def : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), 0, cond,
42 (Select_FPR16_Using_CC_GPR GPR:$lhs, (XLenVT X0),
59 def : Pat<(bf16 (riscv_fmv_h_x GPR:$src)), (FMV_H_X GPR:$src)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td443 let MIOperandInfo = (ops GPR, uimm5);
528 [(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;
533 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
534 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
536 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
537 [(set GPR
[all...]
H A DCSKYInstrInfoF2.td61 def f2FLD_S : F2_LDST_S<0b0, "fld", (outs FPR32Op:$vrz), (ins GPR:$rx, uimm8_2:$imm8)>;
63 def f2FLD_D : F2_LDST_D<0b0, "fld", (outs FPR64Op:$vrz), (ins GPR:$rx, uimm8_2:$imm8)>;
66 def f2FST_S : F2_LDST_S<0b1, "fst", (outs), (ins FPR32Op:$vrz, GPR:$rx, uimm8_2:$imm8)>;
68 def f2FST_D : F2_LDST_D<0b1, "fst", (outs), (ins FPR64Op:$vrz, GPR:$rx, uimm8_2:$imm8)>;
72 def f2FSTM_S : F2_LDSTM_S<0b1, 0, "fstm", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
74 def f2FSTM_D : F2_LDSTM_D<0b1, 0, "fstm", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
76 def f2FSTMU_S : F2_LDSTM_S<0b1, 0b100, "fstmu", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
78 def f2FSTMU_D : F2_LDSTM_D<0b1, 0b100, "fstmu", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
82 def f2FLDM_S : F2_LDSTM_S<0b0, 0, "fldm", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
84 def f2FLDM_D : F2_LDSTM_D<0b0, 0, "fldm", (outs), (ins GPR
[all...]
H A DCSKYInstrFormats.td81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
94 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
96 [(set GPR:$rz, ImmType:$imm16)]> {
110 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), ins,
132 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
145 (ins GPR:$rx, operand:$imm2),
172 (ins GPR:$rx, operand:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
184 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
198 : CSKY32Inst<AddrModeNone, 0x39, (outs GPR:$rz),
199 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td234 def GPRMemAtomic : RegisterOperand<GPR> {
674 : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), "$rd, $rj, $rk">;
676 : Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), "$rd, $rj">;
679 : Fmt3RI2<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm2),
682 : Fmt3RI3<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm3),
685 : Fmt2RI5<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm5),
688 : Fmt2RI6<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm6),
691 : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm12),
694 : Fmt2RI16<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm16),
697 : Fmt1RI20<op, (outs GPR:$rd), (ins ImmOpnd:$imm20), "$rd, $imm20">;
[all …]
H A DLoongArchLBTInstrFormats.td28 : LAInst<(outs), (ins GPR:$rj),
39 : LAInst<(outs), (ins GPR:$rj, uimm3:$imm3),
52 : LAInst<(outs), (ins GPR:$rj, uimm4:$imm4),
65 : LAInst<(outs GPR:$rd), (ins uimm4:$imm4),
78 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5),
91 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5, uimm4:$imm4),
106 : LAInst<(outs GPR:$rd), (ins uimm5:$imm5, uimm8:$imm8),
121 : LAInst<(outs), (ins GPR:$rj, uimm6:$imm6),
134 : LAInst<(outs GPR:$rd), (ins uimm8:$imm8),
147 : LAInst<(outs), (ins GPR:$rj, GPR:$rk),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td193 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
205 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
227 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
278 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
282 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
294 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
296 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
303 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
307 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.td423 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
453 def top16Zero: PatLeaf<(i32 GPR:$src), [{
807 let MIOperandInfo = (ops GPR, i32imm);
818 let MIOperandInfo = (ops GPR, GPR, i32imm);
829 let MIOperandInfo = (ops GPR, i32imm);
1152 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
1173 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1229 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1230 // the GPR is purely vestigal at this point.
1251 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td109 let MIOperandInfo = (ops GPR, s16imm);
190 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
206 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
313 (outs GPR:$dst),
314 (ins GPR:$src2, GPR:$src),
316 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
318 (outs GPR:$dst),
319 (ins GPR:$src2, i64imm:$imm),
321 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
365 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_powerpc.h12 #define GPR_OFFSET(regname) (offsetof(GPR, regname))
13 #define FPR_OFFSET(regname) (sizeof(GPR) + offsetof(FPR, regname))
14 #define VMX_OFFSET(regname) (sizeof(GPR) + sizeof(FPR) + offsetof(VMX, regname))
15 #define GPR_SIZE(regname) (sizeof(((GPR *)NULL)->regname))
188 #define GPR GPR64 macro
190 #undef GPR
194 #define GPR GPR32 macro
196 #undef GPR
200 #define GPR GPR64 macro
205 (offsetof(GPR, regname) + (sizeof(((GPR *)NULL)->regname) - GPR_SIZE(reg)))
[all …]

123456789