| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUSubtarget.cpp | 41 #define AMDGPUSubtarget GCNSubtarget
63 GCNSubtarget::~GCNSubtarget() = default;
65 GCNSubtarget &
66 GCNSubtarget::initializeSubtargetDependencies(const Triple &TT, in initializeSubtargetDependencies()
177 void GCNSubtarget::checkSubtargetFeatures(const Function &F) const { in checkSubtargetFeatures()
192 GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, in GCNSubtarget() function in GCNSubtarget
215 unsigned GCNSubtarget::getConstantBusLimit(unsigned Opcode) const { in getConstantBusLimit()
243 bool GCNSubtarget::zeroesHigh16BitsOfDest(unsigned Opcode) const { in zeroesHigh16BitsOfDest()
653 void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, in overrideSchedPolicy()
670 void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const { in mirFileLoaded()
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| H A D | AMDGPUResourceUsageAnalysis.h | 23 class GCNSubtarget; variable
45 int32_t getTotalNumSGPRs(const GCNSubtarget &ST) const;
48 int32_t getTotalNumVGPRs(const GCNSubtarget &ST, int32_t NumAGPR,
50 int32_t getTotalNumVGPRs(const GCNSubtarget &ST) const;
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| H A D | SIFrameLowering.cpp | 79 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getVGPRSpillLaneOrTempRegister()
134 static void buildPrologSpill(const GCNSubtarget &ST, const SIRegisterInfo &TRI, in buildPrologSpill()
157 static void buildEpilogRestore(const GCNSubtarget &ST, in buildEpilogRestore()
228 const GCNSubtarget &ST;
345 ST(MF.getSubtarget<GCNSubtarget>()), MFI(MF.getFrameInfo()), in PrologEpilogSGPRSpillBuilder()
385 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit()
442 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit()
540 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getEntryFunctionReservedScratchRsrcReg()
590 static unsigned getScratchScaleFactor(const GCNSubtarget &ST) { in getScratchScaleFactor()
610 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionPrologue()
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| H A D | AMDGPUPreLegalizerCombiner.cpp | 47 const GCNSubtarget &STI;
56 const GCNSubtarget &STI, MachineDominatorTree *MDT,
79 #define AMDGPUSubtarget GCNSubtarget
86 #define AMDGPUSubtarget GCNSubtarget
95 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) in AMDGPUPreLegalizerCombinerImpl()
273 const GCNSubtarget &STI = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
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| H A D | AMDGPUAsmPrinter.cpp | 159 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionBodyStart()
237 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionBodyEnd()
277 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionEntryLabel()
460 if (MF.getSubtarget<GCNSubtarget>().isWave32()) { in getAmdhsaKernelCodeProperties()
483 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getAmdhsaKernelDescriptor()
536 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
589 Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()), in runOnMachineFunction()
724 const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F); in initializeTargetID()
736 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getFunctionCodeSize()
760 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getSIProgramInfo()
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| H A D | SIMachineFunctionInfo.cpp | 33 const GCNTargetMachine &getTM(const GCNSubtarget *STI) { in getTM()
39 const GCNSubtarget *STI) in SIMachineFunctionInfo()
46 const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI); in SIMachineFunctionInfo()
185 const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>(); in limitOccupancy()
325 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in shiftSpillPhysVGPRsToLowestRange()
367 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocatePhysicalVGPRForSGPRSpills()
410 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocateSGPRSpillToVGPRLane()
451 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocateVGPRSpillToAGPR()
589 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getGITPtrLoReg()
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| H A D | SILowerSGPRSpills.cpp | 93 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in insertCSRSaves()
136 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in insertCSRRestores()
213 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in spillCalleeSavedRegs()
310 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
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| H A D | SIProgramInfo.h | 25 class GCNSubtarget; variable
101 const MCExpr *getComputePGMRSrc1(const GCNSubtarget &ST,
103 const MCExpr *getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST,
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| H A D | GCNVOPDUtils.cpp | 17 #include "GCNSubtarget.h"
43 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>(); in checkVOPDRegConstraints()
159 const GCNSubtarget &ST = DAG->MF.getSubtarget<GCNSubtarget>(); in apply()
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| H A D | AMDGPUAttributor.cpp | 155 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in hasApertureRegs()
161 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in supportsGetDoorbellID()
166 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getFlatWorkGroupSizes()
172 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getMaximumFlatWorkGroupRange()
187 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getWavesPerEU()
195 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getEffectiveWavesPerEU()
200 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getMaxWavesPerEU()
1012 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in addPreloadKernArgHint()
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| H A D | SIProgramInfo.cpp | 79 const GCNSubtarget &ST) { in getComputePGMRSrc1Reg()
100 CallingConv::ID CC, const GCNSubtarget &ST) { in getPGMRSrc1Reg()
164 const MCExpr *SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST, in getComputePGMRSrc1()
175 const GCNSubtarget &ST, in getPGMRSrc1()
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| H A D | AMDGPURegBankCombiner.cpp | 48 const GCNSubtarget &STI;
60 const GCNSubtarget &STI, MachineDominatorTree *MDT,
101 #define AMDGPUSubtarget GCNSubtarget
108 #define AMDGPUSubtarget GCNSubtarget
117 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) in AMDGPURegBankCombinerImpl()
447 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
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| H A D | AMDGPURemoveIncompatibleFunctions.cpp | 83 const SubtargetSubTypeKV *getGPUInfo(const GCNSubtarget &ST, in getGPUInfo()
139 const GCNSubtarget *ST = in checkFunction()
140 static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F)); in checkFunction()
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| H A D | AMDGPUInstructionSelector.h | 22 #define AMDGPUSubtarget GCNSubtarget
38 class GCNSubtarget; variable
51 const GCNSubtarget *Subtarget;
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
365 const GCNSubtarget &STI;
368 #define AMDGPUSubtarget GCNSubtarget
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| H A D | SIFixVGPRCopies.cpp | 53 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
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| H A D | AMDGPUTargetMachine.cpp | 474 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createGCNMaxOccupancyMachineScheduler()
496 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createIterativeGCNMaxOccupancyMachineScheduler()
512 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createIterativeILPMachineScheduler()
889 I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this); in getSubtargetImpl()
935 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createPostMachineScheduler()
1171 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createMachineScheduler()
1192 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createMachineScheduler()
1521 Allocator, F, static_cast<const GCNSubtarget *>(STI)); in createMachineFunctionInfo()
1532 *MFI, *MF.getSubtarget<GCNSubtarget>().getRegisterInfo(), MF); in convertFuncInfoToYAML()
1542 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in parseMachineFunctionInfo()
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| H A D | AMDGPUPostLegalizerCombiner.cpp | 48 const GCNSubtarget &STI;
58 const GCNSubtarget &STI, MachineDominatorTree *MDT,
118 #define AMDGPUSubtarget GCNSubtarget
125 #define AMDGPUSubtarget GCNSubtarget
134 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) in AMDGPUPostLegalizerCombinerImpl()
491 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
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| H A D | AMDGPURegBankSelect.cpp | 63 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in INITIALIZE_PASS_DEPENDENCY()
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| H A D | AMDGPUCallLowering.cpp | 212 const GCNSubtarget &ST = MIRBuilder.getMF().getSubtarget<GCNSubtarget>(); in getStackAddress()
245 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in assignValueToAddress()
514 const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>(); in lowerFormalArgumentsKernel()
599 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); in lowerFormalArguments()
795 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in passSpecialInputs()
1007 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in doCallerAndCalleePassArgsTheSameWay()
1072 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in areCalleeOutgoingArgsTailCallable()
1112 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in isEligibleForTailCallOptimization()
1157 const GCNSubtarget &ST, const SIMachineFunctionInfo &FuncInfo, in handleImplicitCallArguments()
1184 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in lowerTailCall()
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| H A D | AMDGPUInstrInfo.h | 22 class GCNSubtarget; variable
28 explicit AMDGPUInstrInfo(const GCNSubtarget &st);
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| H A D | SILateBranchLowering.cpp | 85 const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>(); in generateEndPgm()
149 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
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| H A D | AMDGPURegisterBankInfo.h | 27 class GCNSubtarget; variable
44 const GCNSubtarget &Subtarget;
166 AMDGPURegisterBankInfo(const GCNSubtarget &STI);
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| H A D | GCNSchedStrategy.h | 24 class GCNSubtarget; variable
174 const GCNSubtarget &ST;
255 const GCNSubtarget &ST;
388 bool sinkTriviallyRematInsts(const GCNSubtarget &ST,
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| H A D | AMDGPULowerKernelArguments.cpp | 31 const GCNSubtarget &ST;
37 PreloadKernelArgInfo(Function &F, const GCNSubtarget &ST) : F(F), ST(ST) { in PreloadKernelArgInfo()
105 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in lowerKernelArguments()
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| H A D | AMDGPUMCInstLower.cpp | 164 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>(); in lowerOperand()
193 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>(); in emitInstruction()
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